2024-03-28T09:37:39Z
https://nagoya.repo.nii.ac.jp/oai
oai:nagoya.repo.nii.ac.jp:00013147
2023-01-16T04:00:05Z
312:313:314
Memory Data Organization for Low-Energy Address Buses
TOMIYAMA, Hiroyuki
TAKADA, Hiroaki
DUTT, Nikil D.
open access
Copyright (C) 2004 IEICE
compilers
embedded processors
memory data organization
low energy
bus encoding
Energy consumption has become one of the most critical constraints in the design of portable multimedia systems. For media applications, address buses between processor and data memory consume a considerable amount of energy due to their large capacitance and frequent accesses. This paper studies impacts of memory data organization on the address bus energy. Our experiments show that the address bus activity is significantly reduced by 50% through exploring memory data organization and encoding address buses.
Institute of Electronics, Information and Communication Engineers
2004-04-01
eng
journal article
VoR
http://hdl.handle.net/2237/15042
https://nagoya.repo.nii.ac.jp/records/13147
0916-8516
IEICE transactions on electronics
E87-C
4
606
612
https://nagoya.repo.nii.ac.jp/record/13147/files/249.pdf
application/pdf
319.8 kB
2018-02-20