2024-03-29T14:50:06Z
https://nagoya.repo.nii.ac.jp/oai
oai:nagoya.repo.nii.ac.jp:02002730
2023-01-16T04:27:26Z
312:313:314
Activation-Aware Slack Assignment Based Mode-Wise Voltage Scaling for Energy Minimization
CHENG, TaiYu
MASUDA, Yutaka
NAGAYAMA, Jun
MOMIYAMA, Yoichi
CHEN, Jun
HASHIMOTO, Masanori
open access
Copyright(C)2022 IEICE
mode-wise voltage-scaling
activation-aware slack assignment
multi-corner multi-mode
downhill simplex method
Reducing power consumption is a crucial factor making industrial designs, such as mobile SoCs, competitive. Voltage scaling (VS) is the classical yet most effective technique that contributes to quadratic power reduction. A recent design technique called activation-aware slack assignment (ASA) enhances the voltage-scaling by allocating the timing margin of critical paths with a stochastic mean-time-to-failure (MTTF) analysis. Meanwhile, such stochastic treatment of timing errors is accepted in limited application domains, such as image processing. This paper proposes a design optimization methodology that achieves a mode-wise voltage-scalable (MWVS) design guaranteeing no timing errors in each mode operation. This work formulates the MWVS design as an optimization problem that minimizes the overall power consumption considering each mode duration, achievable voltage lowering and accompanied circuit overhead explicitly, and explores the solution space with the downhill simplex algorithm that does not require numerical derivation and frequent objective function evaluations. For obtaining a solution, i.e., a design, in the optimization process, we exploit the multi-corner multi-mode design flow in a commercial tool for performing mode-wise ASA with sets of false paths dedicated to individual modes. We applied the proposed design methodology to RISC-V design. Experimental results show that the proposed methodology saves 13% to 20% more power compared to the conventional VS approach and attains 8% to 15% gain from the conventional single-mode ASA. We also found that cycle-by-cycle fine-grained false path identification reduced leakage power by 31% to 42%.
電子情報通信学会
2022-05-13
2022-03-01
eng
journal article
VoR
http://hdl.handle.net/2237/0002002730
https://nagoya.repo.nii.ac.jp/records/2002730
https://doi.org/10.1587/transfun.2021VLP0006
0916-8508
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
E105A
3
497
508
https://nagoya.repo.nii.ac.jp/record/2002730/files/IEICE_CAD_Cheng.pdf
application/pdf
3 MB
2022-05-13