2024-03-28T16:29:16Z
https://nagoya.repo.nii.ac.jp/oai
oai:nagoya.repo.nii.ac.jp:00010261
2023-01-16T03:56:07Z
312:598:599
Improved Policies for Drowsy Caches in Embedded Processors
Zushi, Junpei
31090
Zeng, Gang
31091
Tomiyama, Hiroyuki
31092
Takada, Hiroaki
31093
Inoue, Koji
31094
In the design of embedded systems, especially battery-powered systems, it is important to reduce energy consumption. Cache are now used not only in general-purpose processors but also in embedded processors. As feature sizes shrink, the leakage energy has contributed to a significant portion of total energy consumption. To reduce the leak-age energy of cache, the Drowsy cache was proposed, in which the cache lines are periodically moved to the low-leakage mode without loss of its content. However, when a cache line in the low-leakage mode is accessed, one or more clock cycles are required to transition the cache line back to the normal mode before its content can be accessed. As a result, these penalty cycles may significantly degrade the cache performance, especially in embedded processors without out-of-order execution. In this paper, we propose four mode transition policies which aim at high energy re-duction with the minimum performance degradation. We also compare our policies with existing policies in the context of embedded processors. Experimental results demon-strate the effectiveness of the proposed policies.
journal article
IEEE
2008-01
application/pdf
4th IEEE International Symposium on Electronic Design, Test and Applications (DELTA 2008)
362
367
http://dx.doi.org/10.1109/DELTA.2008.70
http://hdl.handle.net/2237/12081
https://nagoya.repo.nii.ac.jp/record/10261/files/delta2008.pdf
eng
https://doi.org/10.1109/DELTA.2008.70
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