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2023-01-16T03:58:38Z
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Fast Hardware Algorithm for Division in GF(2m) Based on the Extended Euclid's Algorithm With Parallelization of Modular Reductions
Kobayashi, Katsuki
38165
Takagi, Naofumi
38166
Division
Euclid's algorithm
Galois field
hardware algorithm
We propose a fast hardware algorithm for division in GF(2m) based on the extended Euclid's algorithm. The algorithm requires only one iteration to perform the operations that correspond to the ones performed in two iterations of previously reported division algorithms. Since the algorithm performs modular reductions in parallel by changing the order of execution of the operations, a circuit based on this algorithm has almost the same critical path delay as the previously proposed ones. The circuit computes division in m clock cycles, whereas the previously proposed circuits take 2m - 1 or more clock cycles.
journal article
IEEE
2009-08
application/pdf
IEEE Transactions on Circuits and Systems II: Express Briefs
8
56
644
648
http://hdl.handle.net/2237/13911
http://dx.doi.org/10.1109/TCSII.2009.2024253
1549-7747
https://nagoya.repo.nii.ac.jp/record/12035/files/takagi.pdf
eng
https://doi.org/10.1109/TCSII.2009.2024253
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