2024-03-28T10:32:23Z
https://nagoya.repo.nii.ac.jp/oai
oai:nagoya.repo.nii.ac.jp:02002705
2023-01-16T05:09:14Z
312:313:314
A Synthesis Method Based on Multi-Stage Optimization for Power-Efficient Integrated Optical Logic Circuits
MATSUO, Ryosuke
SHIOMI, Jun
ISHIHARA, Tohru
ONODERA, Hidetoshi
SHINYA, Akihiko
NOTOMI, Masaya
binary decision diagram
logic circuit
optical circuit
Optical logic circuits based on integrated nanophotonics attract significant interest due to their ultra-high-speed operation. However, the power dissipation of conventional optical logic circuits is exponential to the number of inputs of target logic functions. This paper proposes a synthesis method reducing power dissipation to a polynomial order of the number of inputs while exploiting the high-speed nature. Our method divides the target logic function into multiple sub-functions with Optical-to-Electrical (OE) converters. Each sub-function has a smaller number of inputs than that of the original function, which enables to exponentially reduce the power dissipated by an optical logic circuit representing the sub-function. The proposed synthesis method can mitigate the OE converter delay overhead by parallelizing sub-functions. We apply the proposed synthesis method to the ISCAS'85 benchmark circuits. The power consumption of the conventional circuits based on the Binary Decision Diagram (BDD) is at least three orders of magnitude larger than that of the optical logic circuits synthesized by the proposed method. The proposed method reduces the power consumption to about 100mW. The delay of almost all the circuits synthesized by the proposed method is kept less than four times the delay of the conventional BDD-based circuit.
departmental bulletin paper
電子情報通信学会
2021-11-01
application/pdf
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
11
E104A
1546
1554
0916-8508
https://nagoya.repo.nii.ac.jp/record/2002705/files/e104-a_11_1546.pdf
eng
https://doi.org/10.1587/transfun.2020KEP0018
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