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"attribute_value_mlt": [{"subitem_description": "VLSIやプリント配線板設計において，配線経路決定を概略配線と詳細配線に分割して行う手法が提案されている．概略配線から詳細配線への変換可能性の検証を行う問題を配線可能性問題という．この検証は配線領域内のカットと呼ばれる線分について，カット上を通過することのできる配線本数（容量）と概略配線でカット上を通過している配線本数（フロー）の比較により行うことができる．主な実行時間は概略配線からフローを求める時間と容量とフローの比較を行う時間である．本論文では効率の良い配線可能性検証のために容量判定グラフの提案を行い，このグラフに含まれる辺についてのみカットとフローの比較を行うことにより配線可能性の検証ができることを示す．また概略配線からフローを求めるためのフロー導出グラフを提案し，このグラフの辺のフローが与えられたならば，容量判定グラフのすべての辺のフローを計算により求めることができることを示す．", "subitem_description_language": "ja", "subitem_description_type": "Abstract"}]}, "item_10_identifier_60": {"attribute_name": "URI", "attribute_value_mlt": [{"subitem_identifier_type": "HDL", "subitem_identifier_uri": "http://hdl.handle.net/2237/12669"}, {"subitem_identifier_type": "URI", "subitem_identifier_uri": "http://www.ieice.org/jpn/trans_online/index.html"}]}, "item_10_publisher_32": {"attribute_name": "出版者", "attribute_value_mlt": [{"subitem_publisher": "電子情報通信学会", "subitem_publisher_language": "ja"}]}, "item_10_relation_43": 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