@article{oai:nagoya.repo.nii.ac.jp:00012014,
 author = {Matsubara, Yutaka and Honda, Shinya and Takada, Hiroaki},
 journal = {2009 International SoC Design Conference (ISOCC)},
 month = {Sep},
 note = {This paper presents a split interrupt routine model for a two-level hierarchical scheduling in order to integrate multiple independently developed applications that consist of tasks and interrupt routines into a shared CPU. In this model, an interrupt routine is split into an Interrupt Handler (IH), providing device-depended service, and an Interrupt Service Task (IST), providing application-specific service. By using this model, a main part of an interrupt routine is handled as a task and become controllable by global EDF scheduling. We implement this model on an actual processor to evaluate the response time and overhead of activating an IST. Furthermore, we analyze the schedulability of the applications including delay caused by interrupt disabled time and propose a simple schedulability test method. This method helps system integrators, such as automotive manufacturers, to quickly determine which applications could be integrated to the system without detail knowledge of each application in the system design phase.},
 pages = {384--387},
 title = {Hierarchical scheduling for integrating real-time applications with interrupt routines},
 year = {2009}
}