{"created":"2021-03-01T06:18:56.837836+00:00","id":12016,"links":{},"metadata":{"_buckets":{"deposit":"27eb3ed7-6eda-4828-b499-8de23cc35e5a"},"_deposit":{"id":"12016","owners":[],"pid":{"revision_id":0,"type":"depid","value":"12016"},"status":"published"},"_oai":{"id":"oai:nagoya.repo.nii.ac.jp:00012016","sets":["320:321:322"]},"author_link":["38084","38085"],"item_10_biblio_info_6":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2009-10-04","bibliographicIssueDateType":"Issued"},"bibliographicPageEnd":"245","bibliographicPageStart":"238","bibliographic_titles":[{"bibliographic_title":"IEEE International Conference on Computer Design(ICCD 2009)","bibliographic_titleLang":"en"}]}]},"item_10_description_4":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"Two-step physical register deallocation (TSD) is an architectural scheme, which enhances memory-level parallelism (MLP) by pre-executing instructions. Ideally, the TSD allows MLP under the unlimited number of physical registers to be exploited, and consequently only a small register file is necessary for MLP. In practice, however, the amount of MLP exploitable is limited, because there are cases where pre-execution is not performed or timing of pre-execution is delayed. This is caused by data dependencies among the pre-executed instructions. This paper proposes the use of value prediction to solve these problems. Our way of the value prediction usage has the advantage over the conventional way of the usage for enhancing ILP, that there is no need to recover from misspeculation. Our evaluation results using SPECfp2000 benchmark show that our scheme can achieve equivalent performance to that of the previous TSD scheme without value prediction, with 75% of the register file size.","subitem_description_language":"en","subitem_description_type":"Abstract"}]},"item_10_identifier_60":{"attribute_name":"URI","attribute_value_mlt":[{"subitem_identifier_type":"HDL","subitem_identifier_uri":"http://hdl.handle.net/2237/13892"},{"subitem_identifier_type":"DOI","subitem_identifier_uri":"http://dx.doi.org/10.1109/ICCD.2009.5413149"}]},"item_10_publisher_32":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"IEEE","subitem_publisher_language":"en"}]},"item_10_relation_11":{"attribute_name":"DOI","attribute_value_mlt":[{"subitem_relation_type":"isVersionOf","subitem_relation_type_id":{"subitem_relation_type_id_text":"https://doi.org/10.1109/ICCD.2009.5413149","subitem_relation_type_select":"DOI"}}]},"item_10_rights_12":{"attribute_name":"権利","attribute_value_mlt":[{"subitem_rights":"©2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.","subitem_rights_language":"en"}]},"item_10_select_15":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_select_item":"publisher"}]},"item_10_source_id_7":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1063-6404","subitem_source_identifier_type":"PISSN"}]},"item_10_text_14":{"attribute_name":"フォーマット","attribute_value_mlt":[{"subitem_text_value":"application/pdf"}]},"item_1615787544753":{"attribute_name":"出版タイプ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_970fb48d4fbd8a85","subitem_version_type":"VoR"}]},"item_access_right":{"attribute_name":"アクセス権","attribute_value_mlt":[{"subitem_access_right":"open access","subitem_access_right_uri":"http://purl.org/coar/access_right/c_abf2"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Tanaka, Yusuke","creatorNameLang":"en"}],"nameIdentifiers":[{"nameIdentifier":"38084","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"Ando, Hideki","creatorNameLang":"en"}],"nameIdentifiers":[{"nameIdentifier":"38085","nameIdentifierScheme":"WEKO"}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2018-02-20"}],"displaytype":"detail","filename":"ando.pdf","filesize":[{"value":"178.6 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"ando.pdf","objectType":"fulltext","url":"https://nagoya.repo.nii.ac.jp/record/12016/files/ando.pdf"},"version_id":"76d85e89-1d3a-42c4-9805-5a63accb1cbc"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"journal article","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"Reducing register file size through instruction pre-execution enhanced by value prediction","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Reducing register file size through instruction pre-execution enhanced by value prediction","subitem_title_language":"en"}]},"item_type_id":"10","owner":"1","path":["322"],"pubdate":{"attribute_name":"PubDate","attribute_value":"2010-07-30"},"publish_date":"2010-07-30","publish_status":"0","recid":"12016","relation_version_is_last":true,"title":["Reducing register file size through instruction pre-execution enhanced by value prediction"],"weko_creator_id":"1","weko_shared_id":-1},"updated":"2023-01-16T03:58:39.843072+00:00"}