{"created":"2021-03-01T06:19:02.041137+00:00","id":12098,"links":{},"metadata":{"_buckets":{"deposit":"a2bd0472-fb0e-4077-8f20-34f11ccd2742"},"_deposit":{"id":"12098","owners":[],"pid":{"revision_id":0,"type":"depid","value":"12098"},"status":"published"},"_oai":{"id":"oai:nagoya.repo.nii.ac.jp:00012098","sets":["312:313:314"]},"author_link":["38401","38402","38403","38404","38405"],"item_10_biblio_info_6":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2009-12-09","bibliographicIssueDateType":"Issued"},"bibliographicPageEnd":"295","bibliographicPageStart":"292","bibliographic_titles":[{"bibliographic_title":"International Conference on Field-Programmable Technology (FPT 2009)","bibliographic_titleLang":"en"}]}]},"item_10_description_4":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"In the system-level design of MPSoCs (multi-processor system-on-a-chips), system designers start from describing functionalities of the system as processes and channels, and then decide mapping of them to various processing elements (PEs) including CPUs and dedicated hardware modules. A mapping decision is evaluated by simulation or FPGA-based prototyping. Designers iterate mapping and evaluation until all design requirements are met. We have developed two profilers, a process profiler and a memory profiler, for FPGA-based performance analysis of design candidates. The process profiler records a trace of process activations, while the memory profiler records a trace of channel accesses. According to mapping of processes to PEs, the profilers are automatically configured and instrumented into FPGA-based system prototypes by a system-level design tool that we have developed. Designers therefore need to manually modify neither the system description nor the profilers upon each change of process mapping. In order to demonstrate the effectiveness of our profilers, a case study on MPEG4 decoder design was conducted.","subitem_description_language":"en","subitem_description_type":"Abstract"}]},"item_10_identifier_60":{"attribute_name":"URI","attribute_value_mlt":[{"subitem_identifier_type":"HDL","subitem_identifier_uri":"http://hdl.handle.net/2237/13976"},{"subitem_identifier_type":"DOI","subitem_identifier_uri":"http://dx.doi.org/10.1109/FPT.2009.5377660"}]},"item_10_publisher_32":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"IEEE","subitem_publisher_language":"en"}]},"item_10_relation_11":{"attribute_name":"DOI","attribute_value_mlt":[{"subitem_relation_type":"isVersionOf","subitem_relation_type_id":{"subitem_relation_type_id_text":"https://doi.org/10.1109/FPT.2009.5377660","subitem_relation_type_select":"DOI"}}]},"item_10_relation_8":{"attribute_name":"ISBN","attribute_value_mlt":[{"subitem_relation_type":"isPartOf","subitem_relation_type_id":{"subitem_relation_type_id_text":"978-1-4244-4375-8","subitem_relation_type_select":"ISBN"}}]},"item_10_rights_12":{"attribute_name":"権利","attribute_value_mlt":[{"subitem_rights":"©2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE.","subitem_rights_language":"en"}]},"item_10_select_15":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_select_item":"publisher"}]},"item_10_text_14":{"attribute_name":"フォーマット","attribute_value_mlt":[{"subitem_text_value":"application/pdf"}]},"item_1615787544753":{"attribute_name":"出版タイプ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_970fb48d4fbd8a85","subitem_version_type":"VoR"}]},"item_access_right":{"attribute_name":"アクセス権","attribute_value_mlt":[{"subitem_access_right":"open access","subitem_access_right_uri":"http://purl.org/coar/access_right/c_abf2"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Shibata, Seiya","creatorNameLang":"en"}],"nameIdentifiers":[{"nameIdentifier":"38401","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"Ando, Yuki","creatorNameLang":"en"}],"nameIdentifiers":[{"nameIdentifier":"38402","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"Honda, Shinya","creatorNameLang":"en"}],"nameIdentifiers":[{"nameIdentifier":"38403","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"Tomiyama, Hiroyuki","creatorNameLang":"en"}],"nameIdentifiers":[{"nameIdentifier":"38404","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"Takada, Hiroaki","creatorNameLang":"en"}],"nameIdentifiers":[{"nameIdentifier":"38405","nameIdentifierScheme":"WEKO"}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2018-02-20"}],"displaytype":"detail","filename":"honda.pdf","filesize":[{"value":"594.3 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"honda.pdf","objectType":"fulltext","url":"https://nagoya.repo.nii.ac.jp/record/12098/files/honda.pdf"},"version_id":"db4f6e94-047b-41b1-bf1e-46c51f05b630"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"journal article","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"Automatic instrumentation of profilers for FPGA-based design space exploration","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"Automatic instrumentation of profilers for FPGA-based design space exploration","subitem_title_language":"en"}]},"item_type_id":"10","owner":"1","path":["314"],"pubdate":{"attribute_name":"PubDate","attribute_value":"2010-08-05"},"publish_date":"2010-08-05","publish_status":"0","recid":"12098","relation_version_is_last":true,"title":["Automatic instrumentation of profilers for FPGA-based design space exploration"],"weko_creator_id":"1","weko_shared_id":-1},"updated":"2023-01-16T03:58:43.721261+00:00"}