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Register File Size Reduction through Instruction Pre-Execution Incorporating Value Prediction
http://hdl.handle.net/2237/14941
http://hdl.handle.net/2237/1494162d2e467-4f39-4370-a2cc-6c0a15d5d158
名前 / ファイル | ライセンス | アクション |
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Item type | 学術雑誌論文 / Journal Article(1) | |||||
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公開日 | 2011-06-24 | |||||
タイトル | ||||||
タイトル | Register File Size Reduction through Instruction Pre-Execution Incorporating Value Prediction | |||||
言語 | en | |||||
著者 |
TANAKA, Yusuke
× TANAKA, Yusuke× ANDO, Hideki |
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アクセス権 | ||||||
アクセス権 | open access | |||||
アクセス権URI | http://purl.org/coar/access_right/c_abf2 | |||||
権利 | ||||||
言語 | en | |||||
権利情報 | Copyright (C) 2010 IEICE | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | microarchitecture | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | microprocessor | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | instruction pre-execution | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | value prediction | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | register file | |||||
抄録 | ||||||
内容記述 | Two-step physical register deallocation (TSD) is an architectural scheme that enhances memory-level parallelism (MLP) by pre-executing instructions. Ideally, TSD allows exploitation of MLP under an unlimited number of physical registers, and consequently only a small register file is needed for MLP. In practice, however, the amount of MLP exploitable is limited, because there are cases where either 1) pre-execution is not performed; or 2) the timing of pre-execution is delayed. Both are due to data dependencies among the pre-executed instructions. This paper proposes the use of value prediction to solve these problems. This paper proposes the use of value prediction to solve these problems. Evaluation results using the SPECfp2000 benchmark confirm that the proposed scheme with value prediction for predicting addresses achieves equivalent IPC, with a smaller register file, to the previous TSD scheme. The reduction rate of the register file size is 21%. | |||||
言語 | en | |||||
内容記述タイプ | Abstract | |||||
出版者 | ||||||
言語 | en | |||||
出版者 | Institute of Electronics, Information and Communication Engineers | |||||
言語 | ||||||
言語 | eng | |||||
資源タイプ | ||||||
資源タイプresource | http://purl.org/coar/resource_type/c_6501 | |||||
タイプ | journal article | |||||
出版タイプ | ||||||
出版タイプ | VoR | |||||
出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||
関連情報 | ||||||
関連タイプ | isVersionOf | |||||
識別子タイプ | URI | |||||
関連識別子 | http://www.ieice.org/jpn/trans_online/index.html | |||||
ISSN | ||||||
収録物識別子タイプ | PISSN | |||||
収録物識別子 | 0916-8532 | |||||
書誌情報 |
en : IEICE Transactions on Information and Systems 巻 E93-D, 号 12, p. 3294-3305, 発行日 2010-12-01 |
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著者版フラグ | ||||||
値 | publisher | |||||
URI | ||||||
識別子 | http://hdl.handle.net/2237/14941 | |||||
識別子タイプ | HDL | |||||
URI | ||||||
識別子 | http://www.ieice.org/jpn/trans_online/index.html | |||||
識別子タイプ | URI |