@article{oai:nagoya.repo.nii.ac.jp:00013172,
 author = {ISO, Naoyuki and KAWAGUCHI, Yasushi and HIRATA, Tomio},
 issue = {10},
 journal = {IEICE transactions on fundamentals of electronics, communications and computer sciences},
 month = {Oct},
 note = {In VLSI and printed wiring board design, routing process usually consists of two stages: the global routing and the detailed routing. The routability checking is to decide whether the global wires can be transformed into the detailed ones or not. In this paper, we propose two graphs, the capacity checking graph and the initial flow graph, for efficient routability checking in planar layouts.},
 pages = {1878--1882},
 title = {Efficient Routability Checking for Global Wires in Planar Layouts},
 volume = {E80-A},
 year = {1997}
}