{"created":"2021-03-01T06:29:20.864091+00:00","id":21657,"links":{},"metadata":{"_buckets":{"deposit":"6b51921e-98ee-43b0-90d7-5f98727a40f9"},"_deposit":{"id":"21657","owners":[],"pid":{"revision_id":0,"type":"depid","value":"21657"},"status":"published"},"_oai":{"id":"oai:nagoya.repo.nii.ac.jp:00021657","sets":["320:321:322"]},"author_link":["63887","63888","63889","63890","63891","63892","63893","63894"],"item_10_alternative_title_19":{"attribute_name":"その他のタイトル","attribute_value_mlt":[{"subitem_alternative_title":"Design and Evaluation of the 2-bit Bit-Slice Adder Based on 10kA/cm^2 Process","subitem_alternative_title_language":"en"}]},"item_10_biblio_info_6":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2013-07","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"149","bibliographicPageEnd":"16","bibliographicPageStart":"11","bibliographicVolumeNumber":"113","bibliographic_titles":[{"bibliographic_title":"電子情報通信学会技術研究報告. SCE, 超伝導エレクトロニクス","bibliographic_titleLang":"ja"}]}]},"item_10_description_4":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"現在、様々な研究機関で単一磁束量子(Single Flux Quantum, SFQ)論理回路を用いたディジタル回路の研究が行われている。その中で、我々はマイクロプロセッサの研究を行っている。これまで実証されたSFQマイクロプロセッサでは、ビットシリアル・アーキテクチャが用いられてきた。そこで、マイクロプロセッサのさらなる性能向上のため、ビットスライス・アーキテクチャの導入を念頭にビットスライス・アダーの設計を行った。本稿では、ビットパラレル、シリアル、スライス・アーキテクチャを紹介し、それらに基づくアダーの性能を演算時間と回路規模から比較し評価した。またビット・スライス幅が2ビットのビットスライス・アダーを設計し、AIST 10kA/cm^2 Nbアドバンストプロセスを用いて試作を行い、高速試験において動作実証に成功したので報告する。 ","subitem_description_language":"ja","subitem_description_type":"Abstract"},{"subitem_description":"A large number of researches on designing digital circuits by using SFQ logic circuits have been undertaken extensively. We have been developing SFQ microprocessors. In our demonstrated SFQ microprocessors, bit serial architectures were used. In order to increase the performance of the microprocessors, we have designed a bit-slice adder toward introduction of a bit-slice architecture. In this paper, we present a bit-parallel, serial, and slice architectures, and we compare and evaluate the operating times and circuit sizes of the adders based on these architectures. We also report design of a 2-bit bit-slice adder using AIST 10 kA/cm^2 niobium advanced process, and demonstration of its high-speed operation.","subitem_description_language":"en","subitem_description_type":"Abstract"}]},"item_10_description_5":{"attribute_name":"内容記述","attribute_value_mlt":[{"subitem_description":"(信号処理基盤技術及びその応用,一般)","subitem_description_language":"ja","subitem_description_type":"Other"},{"subitem_description":"IEICE Technical Report;SCE2013-12","subitem_description_language":"en","subitem_description_type":"Other"}]},"item_10_identifier_60":{"attribute_name":"URI","attribute_value_mlt":[{"subitem_identifier_type":"URI","subitem_identifier_uri":"http://ci.nii.ac.jp/naid/110009778168/"},{"subitem_identifier_type":"HDL","subitem_identifier_uri":"http://hdl.handle.net/2237/23805"}]},"item_10_publisher_32":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"一般社団法人電子情報通信学会","subitem_publisher_language":"ja"}]},"item_10_relation_40":{"attribute_name":"シリーズ","attribute_value_mlt":[{"subitem_relation_name":[{"subitem_relation_name_text":"IEICE Technical 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Yuhi","creatorNameLang":"en"}],"nameIdentifiers":[{"nameIdentifier":"63892","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"TANAKA, Masamitsu","creatorNameLang":"en"}],"nameIdentifiers":[{"nameIdentifier":"63893","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"FUJIMAKI, Akira","creatorNameLang":"en"}],"nameIdentifiers":[{"nameIdentifier":"63894","nameIdentifierScheme":"WEKO"}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2018-06-01"}],"displaytype":"detail","filename":"110009778168.pdf","filesize":[{"value":"822.6 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