{"_buckets": {"deposit": "0e17d878-2fbd-4041-b2de-236220f36aa4"}, "_deposit": {"id": "3868", "owners": [], "pid": {"revision_id": 0, "type": "depid", "value": "3868"}, "status": "published"}, "_oai": {"id": "oai:nagoya.repo.nii.ac.jp:00003868", "sets": []}, "author_link": ["9766", "9767"], "item_10_biblio_info_6": {"attribute_name": "\u66f8\u8a8c\u60c5\u5831", "attribute_value_mlt": [{"bibliographicIssueDates": {"bibliographicIssueDate": "2005-01", "bibliographicIssueDateType": "Issued"}, "bibliographicIssueNumber": "1", "bibliographicPageEnd": "21", "bibliographicPageStart": "12", "bibliographicVolumeNumber": "54", "bibliographic_titles": [{"bibliographic_title": "IEEE Transactions on computers", "bibliographic_titleLang": "en"}]}]}, "item_10_description_4": {"attribute_name": "\u6284\u9332", "attribute_value_mlt": [{"subitem_description": "A mixed radix-4/2 algorithm for modular multiplication/division suitable for VLSI implementation is proposed. The algorithm is based on Montgomery method for modular multiplication and on the extended Binary GCD algorithm for modular division. Both algorithms are modified and combined into the proposed algorithm so that almost all the hardware components are shared. The new algorithm carries out both calculations using simple operations such as shifts, additions, and subtractions. The radix-2 signed-digit representation is used to avoid carry propagation in all additions and subtractions. A modular multiplier/divider based on the algorithm performs an n-bit modular multiplication/division in O(n) clock cycles where the length of the clock cycle is constant and independent of n. The modular multiplier/divider has a linear array structure with a bit-slice feature and can be implemented with much smaller hardware than that necessary to implement both multiplier and divider separately.", "subitem_description_language": "en", "subitem_description_type": "Abstract"}]}, "item_10_identifier_60": {"attribute_name": "URI", "attribute_value_mlt": [{"subitem_identifier_type": "HDL", "subitem_identifier_uri": "http://hdl.handle.net/2237/5293"}]}, "item_10_publisher_32": {"attribute_name": "\u51fa\u7248\u8005", "attribute_value_mlt": [{"subitem_publisher": "IEEE", "subitem_publisher_language": "en"}]}, "item_10_relation_11": {"attribute_name": "DOI", "attribute_value_mlt": [{"subitem_relation_type": "isVersionOf", "subitem_relation_type_id": {"subitem_relation_type_id_text": "http://doi.org/10.1109/TC.2005.1", "subitem_relation_type_select": "DOI"}}]}, "item_10_rights_12": {"attribute_name": "\u6a29\u5229", "attribute_value_mlt": [{"subitem_rights": "Copyright c 2005 IEEE. Reprinted from (relevant publication info). This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of Nagoya University\u2019s products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org.", "subitem_rights_language": "en"}]}, "item_10_select_15": {"attribute_name": "\u8457\u8005\u7248\u30d5\u30e9\u30b0", "attribute_value_mlt": [{"subitem_select_item": "publisher"}]}, "item_10_source_id_7": {"attribute_name": "ISSN", "attribute_value_mlt": [{"subitem_source_identifier": "00189340", "subitem_source_identifier_type": "PISSN"}]}, "item_10_text_14": {"attribute_name": "\u30d5\u30a9\u30fc\u30de\u30c3\u30c8", "attribute_value_mlt": [{"subitem_text_value": "application/pdf"}]}, "item_1615787544753": {"attribute_name": "\u51fa\u7248\u30bf\u30a4\u30d7", "attribute_value_mlt": [{"subitem_version_resource": "http://purl.org/coar/version/c_970fb48d4fbd8a85", "subitem_version_type": "VoR"}]}, "item_access_right": {"attribute_name": "\u30a2\u30af\u30bb\u30b9\u6a29", "attribute_value_mlt": [{"subitem_access_right": "open access", "subitem_access_right_uri": "http://purl.org/coar/access_right/c_abf2"}]}, "item_creator": {"attribute_name": "\u8457\u8005", "attribute_type": "creator", "attribute_value_mlt": [{"creatorNames": [{"creatorName": "\u9ad8\u6728, \u76f4\u53f2", "creatorNameLang": "ja"}], "nameIdentifiers": [{"nameIdentifier": "9766", "nameIdentifierScheme": "WEKO"}]}, {"creatorNames": [{"creatorName": "Takagi, Naofumi", "creatorNameLang": "en"}], "nameIdentifiers": [{"nameIdentifier": "9767", "nameIdentifierScheme": "WEKO"}]}]}, "item_files": {"attribute_name": "\u30d5\u30a1\u30a4\u30eb\u60c5\u5831", "attribute_type": "file", "attribute_value_mlt": [{"accessrole": "open_date", "date": [{"dateType": "Available", "dateValue": "2018-02-19"}], "displaytype": "detail", "download_preview_message": "", "file_order": 0, "filename": "01362636.pdf", "filesize": [{"value": "1.2 MB"}], "format": "application/pdf", "future_date_message": "", "is_thumbnail": false, "licensetype": "license_note", "mimetype": "application/pdf", "size": 1200000.0, "url": {"label": "01362636.pdf", "objectType": "fulltext", "url": "https://nagoya.repo.nii.ac.jp/record/3868/files/01362636.pdf"}, "version_id": "529d3d6c-b5d5-41ae-b93c-785c2f6a4909"}]}, "item_keyword": {"attribute_name": "\u30ad\u30fc\u30ef\u30fc\u30c9", "attribute_value_mlt": [{"subitem_subject": "Computer arithmetic", "subitem_subject_scheme": "Other"}, {"subitem_subject": "hardware algorithm", "subitem_subject_scheme": "Other"}, {"subitem_subject": "modular multiplication", "subitem_subject_scheme": "Other"}, {"subitem_subject": "modular division", "subitem_subject_scheme": "Other"}, {"subitem_subject": "redundant representation", "subitem_subject_scheme": "Other"}, {"subitem_subject": "cryptography", "subitem_subject_scheme": "Other"}]}, "item_language": {"attribute_name": "\u8a00\u8a9e", "attribute_value_mlt": [{"subitem_language": "eng"}]}, "item_resource_type": {"attribute_name": "\u8cc7\u6e90\u30bf\u30a4\u30d7", "attribute_value_mlt": [{"resourcetype": "journal article", "resourceuri": "http://purl.org/coar/resource_type/c_6501"}]}, "item_title": "A hardware algorithm for modular multiplication/division", "item_titles": {"attribute_name": "\u30bf\u30a4\u30c8\u30eb", "attribute_value_mlt": [{"subitem_title": "A hardware algorithm for modular multiplication/division", "subitem_title_language": "en"}]}, "item_type_id": "10", "owner": "1", "path": ["312/313/314"], "permalink_uri": "http://hdl.handle.net/2237/5293", "pubdate": {"attribute_name": "PubDate", "attribute_value": "2006-01-10"}, "publish_date": "2006-01-10", "publish_status": "0", "recid": "3868", "relation": {}, "relation_version_is_last": true, "title": ["A hardware algorithm for modular multiplication/division"], "weko_shared_id": -1}