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A hardware algorithm for modular multiplication/division
http://hdl.handle.net/2237/5293
http://hdl.handle.net/2237/529363f40b3b-52fa-4c2b-ae3f-db50b97692b8
名前 / ファイル | ライセンス | アクション |
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Item type | 学術雑誌論文 / Journal Article(1) | |||||
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公開日 | 2006-01-10 | |||||
タイトル | ||||||
タイトル | A hardware algorithm for modular multiplication/division | |||||
言語 | en | |||||
著者 |
高木, 直史
× 高木, 直史× Takagi, Naofumi |
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アクセス権 | ||||||
アクセス権 | open access | |||||
アクセス権URI | http://purl.org/coar/access_right/c_abf2 | |||||
権利 | ||||||
言語 | en | |||||
権利情報 | Copyright c 2005 IEEE. Reprinted from (relevant publication info). This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of Nagoya University’s products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | Computer arithmetic | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | hardware algorithm | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | modular multiplication | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | modular division | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | redundant representation | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | cryptography | |||||
抄録 | ||||||
内容記述 | A mixed radix-4/2 algorithm for modular multiplication/division suitable for VLSI implementation is proposed. The algorithm is based on Montgomery method for modular multiplication and on the extended Binary GCD algorithm for modular division. Both algorithms are modified and combined into the proposed algorithm so that almost all the hardware components are shared. The new algorithm carries out both calculations using simple operations such as shifts, additions, and subtractions. The radix-2 signed-digit representation is used to avoid carry propagation in all additions and subtractions. A modular multiplier/divider based on the algorithm performs an n-bit modular multiplication/division in O(n) clock cycles where the length of the clock cycle is constant and independent of n. The modular multiplier/divider has a linear array structure with a bit-slice feature and can be implemented with much smaller hardware than that necessary to implement both multiplier and divider separately. | |||||
言語 | en | |||||
内容記述タイプ | Abstract | |||||
出版者 | ||||||
言語 | en | |||||
出版者 | IEEE | |||||
言語 | ||||||
言語 | eng | |||||
資源タイプ | ||||||
資源タイプresource | http://purl.org/coar/resource_type/c_6501 | |||||
タイプ | journal article | |||||
出版タイプ | ||||||
出版タイプ | VoR | |||||
出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||
DOI | ||||||
関連タイプ | isVersionOf | |||||
識別子タイプ | DOI | |||||
関連識別子 | http://doi.org/10.1109/TC.2005.1 | |||||
ISSN | ||||||
収録物識別子タイプ | PISSN | |||||
収録物識別子 | 00189340 | |||||
書誌情報 |
en : IEEE Transactions on computers 巻 54, 号 1, p. 12-21, 発行日 2005-01 |
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フォーマット | ||||||
application/pdf | ||||||
著者版フラグ | ||||||
値 | publisher | |||||
URI | ||||||
識別子 | http://hdl.handle.net/2237/5293 | |||||
識別子タイプ | HDL |