{"created":"2021-03-01T06:16:08.752678+00:00","id":9381,"links":{},"metadata":{"_buckets":{"deposit":"7037c47a-47a1-459c-ad72-94ce22e223c3"},"_deposit":{"id":"9381","owners":[],"pid":{"revision_id":0,"type":"depid","value":"9381"},"status":"published"},"_oai":{"id":"oai:nagoya.repo.nii.ac.jp:00009381","sets":["312:313:314"]},"author_link":["26839","26840","26841"],"item_10_biblio_info_6":{"attribute_name":"書誌情報","attribute_value_mlt":[{"bibliographicIssueDates":{"bibliographicIssueDate":"2008-11","bibliographicIssueDateType":"Issued"},"bibliographicIssueNumber":"11","bibliographicPageEnd":"1148","bibliographicPageStart":"1144","bibliographicVolumeNumber":"55","bibliographic_titles":[{"bibliographic_title":"IEEE Transactions on Circuits and Systems II: Express Briefs","bibliographic_titleLang":"en"}]}]},"item_10_description_4":{"attribute_name":"抄録","attribute_value_mlt":[{"subitem_description":"A combined circuit for multiplication and inversion in ${rm GF}(2^{m})$ is proposed. In order to develop a combined circuit, we start with combining the most significant bit first multiplication algorithm and the modified extended Euclid's algorithm by focusing on the similarities between them. Since almost all hardware components of the circuits are shared by multiplication and inversion, the combined circuit can be implemented with significantly smaller hardware than that necessary to implement both multiplication and inversion separately. By logic synthesis, the area of the proposed circuit is estimated to be approximately over 15% smaller than that of previously proposed combined multiplication/division circuits.","subitem_description_language":"en","subitem_description_type":"Abstract"}]},"item_10_identifier_60":{"attribute_name":"URI","attribute_value_mlt":[{"subitem_identifier_type":"HDL","subitem_identifier_uri":"http://hdl.handle.net/2237/11157"}]},"item_10_publisher_32":{"attribute_name":"出版者","attribute_value_mlt":[{"subitem_publisher":"IEEE","subitem_publisher_language":"en"}]},"item_10_relation_11":{"attribute_name":"DOI","attribute_value_mlt":[{"subitem_relation_type":"isVersionOf","subitem_relation_type_id":{"subitem_relation_type_id_text":"https://doi.org/10.1109/TCSII.2008.2003347","subitem_relation_type_select":"DOI"}}]},"item_10_rights_12":{"attribute_name":"権利","attribute_value_mlt":[{"subitem_rights":"Copyright © 2008 IEEE. Reprinted from IEEE Transactions on Circuits and Systems II: Express Briefs, v.55, n.11, 2008, p.1144-1148. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of Nagoya University’s products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org.","subitem_rights_language":"en"}]},"item_10_select_15":{"attribute_name":"著者版フラグ","attribute_value_mlt":[{"subitem_select_item":"publisher"}]},"item_10_source_id_7":{"attribute_name":"ISSN","attribute_value_mlt":[{"subitem_source_identifier":"1549-7747","subitem_source_identifier_type":"PISSN"}]},"item_10_text_14":{"attribute_name":"フォーマット","attribute_value_mlt":[{"subitem_text_value":"application/pdf"}]},"item_1615787544753":{"attribute_name":"出版タイプ","attribute_value_mlt":[{"subitem_version_resource":"http://purl.org/coar/version/c_970fb48d4fbd8a85","subitem_version_type":"VoR"}]},"item_access_right":{"attribute_name":"アクセス権","attribute_value_mlt":[{"subitem_access_right":"open access","subitem_access_right_uri":"http://purl.org/coar/access_right/c_abf2"}]},"item_creator":{"attribute_name":"著者","attribute_type":"creator","attribute_value_mlt":[{"creatorNames":[{"creatorName":"Kobayashi, Katsuki","creatorNameLang":"en"}],"nameIdentifiers":[{"nameIdentifier":"26839","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"Takagi, Naofumi","creatorNameLang":"en"}],"nameIdentifiers":[{"nameIdentifier":"26840","nameIdentifierScheme":"WEKO"}]},{"creatorNames":[{"creatorName":"高木, 直史","creatorNameLang":"ja"}],"nameIdentifiers":[{"nameIdentifier":"26841","nameIdentifierScheme":"WEKO"}]}]},"item_files":{"attribute_name":"ファイル情報","attribute_type":"file","attribute_value_mlt":[{"accessrole":"open_date","date":[{"dateType":"Available","dateValue":"2018-02-20"}],"displaytype":"detail","filename":"getPDF_jsp.pdf","filesize":[{"value":"494.5 kB"}],"format":"application/pdf","licensetype":"license_note","mimetype":"application/pdf","url":{"label":"getPDF_jsp.pdf","objectType":"fulltext","url":"https://nagoya.repo.nii.ac.jp/record/9381/files/getPDF_jsp.pdf"},"version_id":"d0781c5e-306b-40eb-8980-8ed9872dc93b"}]},"item_keyword":{"attribute_name":"キーワード","attribute_value_mlt":[{"subitem_subject":"Galois field","subitem_subject_scheme":"Other"},{"subitem_subject":"inversion","subitem_subject_scheme":"Other"},{"subitem_subject":"multiplication","subitem_subject_scheme":"Other"}]},"item_language":{"attribute_name":"言語","attribute_value_mlt":[{"subitem_language":"eng"}]},"item_resource_type":{"attribute_name":"資源タイプ","attribute_value_mlt":[{"resourcetype":"journal article","resourceuri":"http://purl.org/coar/resource_type/c_6501"}]},"item_title":"A Combined Circuit for Multiplication and Inversion in ${rm GF}(2^{m})$","item_titles":{"attribute_name":"タイトル","attribute_value_mlt":[{"subitem_title":"A Combined Circuit for Multiplication and Inversion in ${rm GF}(2^{m})$","subitem_title_language":"en"}]},"item_type_id":"10","owner":"1","path":["314"],"pubdate":{"attribute_name":"PubDate","attribute_value":"2009-02-24"},"publish_date":"2009-02-24","publish_status":"0","recid":"9381","relation_version_is_last":true,"title":["A Combined Circuit for Multiplication and Inversion in ${rm GF}(2^{m})$"],"weko_creator_id":"1","weko_shared_id":-1},"updated":"2023-01-16T03:54:46.789301+00:00"}