| Item type |
itemtype_ver1(1) |
| 公開日 |
2022-05-13 |
| タイトル |
|
|
タイトル |
Activation-Aware Slack Assignment Based Mode-Wise Voltage Scaling for Energy Minimization |
|
言語 |
en |
| 著者 |
CHENG, TaiYu
MASUDA, Yutaka
NAGAYAMA, Jun
MOMIYAMA, Yoichi
CHEN, Jun
HASHIMOTO, Masanori
|
| アクセス権 |
|
|
アクセス権 |
open access |
|
アクセス権URI |
http://purl.org/coar/access_right/c_abf2 |
| 権利 |
|
|
言語 |
en |
|
権利情報 |
Copyright(C)2022 IEICE |
| キーワード |
|
|
主題Scheme |
Other |
|
主題 |
mode-wise voltage-scaling |
| キーワード |
|
|
主題Scheme |
Other |
|
主題 |
activation-aware slack assignment |
| キーワード |
|
|
主題Scheme |
Other |
|
主題 |
multi-corner multi-mode |
| キーワード |
|
|
主題Scheme |
Other |
|
主題 |
downhill simplex method |
| 内容記述 |
|
|
内容記述タイプ |
Abstract |
|
内容記述 |
Reducing power consumption is a crucial factor making industrial designs, such as mobile SoCs, competitive. Voltage scaling (VS) is the classical yet most effective technique that contributes to quadratic power reduction. A recent design technique called activation-aware slack assignment (ASA) enhances the voltage-scaling by allocating the timing margin of critical paths with a stochastic mean-time-to-failure (MTTF) analysis. Meanwhile, such stochastic treatment of timing errors is accepted in limited application domains, such as image processing. This paper proposes a design optimization methodology that achieves a mode-wise voltage-scalable (MWVS) design guaranteeing no timing errors in each mode operation. This work formulates the MWVS design as an optimization problem that minimizes the overall power consumption considering each mode duration, achievable voltage lowering and accompanied circuit overhead explicitly, and explores the solution space with the downhill simplex algorithm that does not require numerical derivation and frequent objective function evaluations. For obtaining a solution, i.e., a design, in the optimization process, we exploit the multi-corner multi-mode design flow in a commercial tool for performing mode-wise ASA with sets of false paths dedicated to individual modes. We applied the proposed design methodology to RISC-V design. Experimental results show that the proposed methodology saves 13% to 20% more power compared to the conventional VS approach and attains 8% to 15% gain from the conventional single-mode ASA. We also found that cycle-by-cycle fine-grained false path identification reduced leakage power by 31% to 42%. |
|
言語 |
en |
| 出版者 |
|
|
出版者 |
電子情報通信学会 |
|
言語 |
ja |
| 言語 |
|
|
言語 |
eng |
| 資源タイプ |
|
|
資源タイプresource |
http://purl.org/coar/resource_type/c_6501 |
|
タイプ |
journal article |
| 出版タイプ |
|
|
出版タイプ |
VoR |
|
出版タイプResource |
http://purl.org/coar/version/c_970fb48d4fbd8a85 |
| 関連情報 |
|
|
関連タイプ |
isVersionOf |
|
|
識別子タイプ |
DOI |
|
|
関連識別子 |
https://doi.org/10.1587/transfun.2021VLP0006 |
| 収録物識別子 |
|
|
収録物識別子タイプ |
PISSN |
|
収録物識別子 |
0916-8508 |
| 書誌情報 |
en : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
巻 E105A,
号 3,
p. 497-508,
発行日 2022-03-01
|
| ファイル公開日 |
|
|
日付 |
2022-05-13 |
|
日付タイプ |
Available |
IEICE_CAD_Cheng.pdf (3 MB)
