| Item type |
itemtype_ver1(1) |
| 公開日 |
2022-05-13 |
| タイトル |
|
|
タイトル |
Low-Power Design Methodology of Voltage Over-Scalable Circuit with Critical Path Isolation and Bit-Width Scaling |
|
言語 |
en |
| 著者 |
MASUDA, Yutaka
NAGAYAMA, Jun
CHENG, TaiYu
ISHIHARA, Tohru
MOMIYAMA, Yoichi
HASHIMOTO, Masanori
|
| アクセス権 |
|
|
アクセス権 |
open access |
|
アクセス権URI |
http://purl.org/coar/access_right/c_abf2 |
| 権利 |
|
|
言語 |
en |
|
権利情報 |
Copyright(C)2022 IEICE |
| キーワード |
|
|
主題Scheme |
Other |
|
主題 |
critical path isolation |
| キーワード |
|
|
主題Scheme |
Other |
|
主題 |
bit-width scaling |
| キーワード |
|
|
主題Scheme |
Other |
|
主題 |
voltage over-scaling |
| キーワード |
|
|
主題Scheme |
Other |
|
主題 |
approximate computing |
| 内容記述 |
|
|
内容記述タイプ |
Abstract |
|
内容記述 |
This work proposes a design methodology that saves the power dissipation under voltage over-scaling (VOS) operation. The key idea of the proposed design methodology is to combine critical path isolation (CPI) and bit-width scaling (BWS) under the constraint of computational quality, e.g., Peak Signal-to-Noise Ratio (PSNR) in the image processing domain. Conventional CPI inherently cannot reduce the delay of intrinsic critical paths (CPs), which may significantly restrict the power saving effect. On the other hand, the proposed methodology tries to reduce both intrinsic and non-intrinsic CPs. Therefore, our design dramatically reduces the supply voltage and power dissipation while satisfying the quality constraint. Moreover, for reducing co-design exploration space, the proposed methodology utilizes the exclusiveness of the paths targeted by CPI and BWS, where CPI aims at reducing the minimum supply voltage of non-intrinsic CP, and BWS focuses on intrinsic CPs in arithmetic units. From this key exclusiveness, the proposed design splits the simultaneous optimization problem into three sub-problems; (1) the determination of bit-width reduction, (2) the timing optimization for non-intrinsic CPs, and (3) investigating the minimum supply voltage of the BWS and CPI-applied circuit under quality constraint, for reducing power dissipation. Thanks to the problem splitting, the proposed methodology can efficiently find quality-constrained minimum-power design. Evaluation results show that CPI and BWS are highly compatible, and they significantly enhance the efficacy of VOS. In a case study of a GPGPU processor, the proposed design saves the power dissipation by 42.7% with an image processing workload and by 51.2% with a neural network inference workload. |
|
言語 |
en |
| 出版者 |
|
|
出版者 |
電子情報通信学会 |
|
言語 |
ja |
| 言語 |
|
|
言語 |
eng |
| 資源タイプ |
|
|
資源タイプresource |
http://purl.org/coar/resource_type/c_6501 |
|
タイプ |
journal article |
| 出版タイプ |
|
|
出版タイプ |
VoR |
|
出版タイプResource |
http://purl.org/coar/version/c_970fb48d4fbd8a85 |
| 関連情報 |
|
|
関連タイプ |
isVersionOf |
|
|
識別子タイプ |
DOI |
|
|
関連識別子 |
https://doi.org/10.1587/transfun.2021VLP0002 |
| 収録物識別子 |
|
|
収録物識別子タイプ |
PISSN |
|
収録物識別子 |
0916-8508 |
| 書誌情報 |
en : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
巻 E105A,
号 3,
p. 509-517,
発行日 2022-03-01
|
| ファイル公開日 |
|
|
日付 |
2022-05-13 |
|
日付タイプ |
Available |
IEICE_CAD_Masuda.pdf (3 MB)
