| Item type |
itemtype_ver1(1) |
| 公開日 |
2022-05-13 |
| タイトル |
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タイトル |
Critical Path Isolation and Bit-Width Scaling Are Highly Compatible for Voltage Over-Scalable Design |
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言語 |
en |
| 著者 |
Masuda, Yutaka
Nagayama, Jun
Cheng, TaiYu
Ishihara, Tohru
Momiyama, Yoichi
Hashimoto, Masanori
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| アクセス権 |
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アクセス権 |
open access |
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アクセス権URI |
http://purl.org/coar/access_right/c_abf2 |
| 権利 |
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言語 |
en |
|
権利情報 |
“© 2021 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.” |
| 内容記述 |
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内容記述タイプ |
Abstract |
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内容記述 |
This work proposes a design methodology that saves the power under voltage over-scaling (VOS) operation. The key idea of the proposed design methodology is to combine critical path isolation (CPI) and bit-width scaling (BWS) under the constraint of computational quality, e.g., Peak Signal-to-Noise Ratio (PSNR). Conventional CPI inherently cannot reduce the delay of intrinsic critical paths (CPs), which may significantly restrict the power saving effect. On the other hand, the proposed methodology tries to reduce both intrinsic and non-intrinsic CPs. Therefore, our design dramatically reduces the supply voltage and power dissipation while satisfying the quality constraint. Moreover, for reducing co-design exploration space, the proposed methodology utilizes the exclusiveness of the paths targeted by CPI and BWS, where CPI aims at reducing the minimum supply voltage of non-intrinsic CP, and BWS focuses on intrinsic CPs in arithmetic units. From this key exclusiveness, the proposed design splits the simultaneous optimization problem into three sub-problems; (1) the determination of bit-width reduction, (2) the timing optimization for non-intrinsic CPs, and (3) investigating the minimum supply voltage of the BWS and CPI-applied circuit under quality constraint, for reducing power dissipation. Thanks to the problem splitting, the proposed methodology can efficiently find quality-constrained minimum-power design. Evaluation results show that CPI and BWS are highly compatible, and they significantly enhance the efficacy of VOS. In a case study of GPGPU processor, the proposed design saves the power dissipation by 42.7% for an image processing and by 51.2% for a neural network inference workload. |
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言語 |
en |
| 内容記述 |
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内容記述タイプ |
Other |
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内容記述 |
DATE 21. 1-5 Feb. 2021. Grenoble, France (Virtual) |
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言語 |
en |
| 出版者 |
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出版者 |
IEEE |
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言語 |
en |
| 言語 |
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言語 |
eng |
| 資源タイプ |
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資源タイプ識別子 |
http://purl.org/coar/resource_type/c_5794 |
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資源タイプ |
conference paper |
| 出版タイプ |
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出版タイプ |
AM |
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出版タイプResource |
http://purl.org/coar/version/c_ab4af688f83e57aa |
| 関連情報 |
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関連タイプ |
isVersionOf |
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識別子タイプ |
DOI |
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関連識別子 |
https://doi.org/10.23919/DATE51398.2021.9473946 |
| 関連情報 |
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関連タイプ |
isPartOf |
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識別子タイプ |
ISBN |
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|
関連識別子 |
978-1-7281-6336-9 |
| 収録物識別子 |
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収録物識別子タイプ |
PISSN |
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収録物識別子 |
1530-1591 |
| 書誌情報 |
en : 2021 Design, Automation & Test in Europe Conference & Exhibition (DATE)
p. 1260-1265,
発行日 2021-07
|
DATE_Masuda_submit.pdf (344 KB)
