| Item type |
itemtype_ver1(1) |
| 公開日 |
2022-05-17 |
| タイトル |
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|
タイトル |
Real-Time Minimum Energy Point Tracking Using a Predetermined Optimal Voltage Setting Strategy |
|
言語 |
en |
| 著者 |
Kiyawat, Khyati
Masuda, Yutaka
Shiomi, Jun
Ishihara, Tohru
|
| アクセス権 |
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|
アクセス権 |
open access |
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アクセス権URI |
http://purl.org/coar/access_right/c_abf2 |
| 権利 |
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|
言語 |
en |
|
権利情報 |
“© 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.” |
| 内容記述 |
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|
内容記述タイプ |
Abstract |
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内容記述 |
Minimizing the energy consumption of processors for a given computational workload is highly desired for matured and energy efficient, information oriented society. In this paper, we refer to a pair of the supply voltage (VDD) and threshold voltage (VTH), which minimizes the energy consumption of the processor under a given computational workload, as a minimum energy point (MEP in short). Since always running at the MEP largely reduces the energy consumption of processors without fundamental degradation of the performance, a lot of methods for tracking the MEP at runtime have been investigated over the past several years. However, to the best of our knowledge, all the previous methods are based on time-consuming power measurement to identify the MEP at runtime, which prevents the real-time tracking of the MEP. This paper proposes a real-time MEP tracking method based on a predetermined MEP-curve which is characterized as a linear model for each chip at a boot phase. Experimental results obtained using a 50-stage fanout-4 inverter chain designed to reflect the behavior of a microprocessor pipeline demonstrate that the energy loss introduced by the linear approximation MEP model is only 3.1% at the worst case. |
|
言語 |
en |
| 内容記述 |
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内容記述タイプ |
Other |
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内容記述 |
2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI). 6-8 July 2020. Limassol, Cyprus |
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言語 |
en |
| 出版者 |
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出版者 |
IEEE |
|
言語 |
en |
| 言語 |
|
|
言語 |
eng |
| 資源タイプ |
|
|
資源タイプresource |
http://purl.org/coar/resource_type/c_6501 |
|
タイプ |
journal article |
| 出版タイプ |
|
|
出版タイプ |
AM |
|
出版タイプResource |
http://purl.org/coar/version/c_ab4af688f83e57aa |
| 関連情報 |
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|
関連タイプ |
isVersionOf |
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|
識別子タイプ |
DOI |
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|
関連識別子 |
https://doi.org/10.1109/ISVLSI49217.2020.00082 |
| 関連情報 |
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|
関連タイプ |
isPartOf |
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|
識別子タイプ |
ISBN |
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|
関連識別子 |
978-1-7281-5775-7 |
| 収録物識別子 |
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収録物識別子タイプ |
PISSN |
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収録物識別子 |
2159-3469 |
| 書誌情報 |
en : Proceedings : 2020 IEEE Computer Society Annual Symposium on VLSI : ISVLSI 2020
p. 415-421,
発行日 2020-08-04
|
ISVLSI_khyati_submit.pdf (4.9 MB)
