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A VLSI algorithm for computing the Euclidean norm of a 3D vector
http://hdl.handle.net/2237/5291
http://hdl.handle.net/2237/529112ba6b0e-d6bd-48a8-880c-86eb76c8399f
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
00888043.pdf (220.6 kB)
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| アイテムタイプ | 学術雑誌論文 / Journal Article(1) | |||||
|---|---|---|---|---|---|---|
| 公開日 | 2006-01-10 | |||||
| タイトル | ||||||
| タイトル | A VLSI algorithm for computing the Euclidean norm of a 3D vector | |||||
| 言語 | en | |||||
| 著者 |
高木, 直史
× 高木, 直史× Takagi, Naofumi |
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| アクセス権 | ||||||
| アクセス権 | open access | |||||
| アクセス権URI | http://purl.org/coar/access_right/c_abf2 | |||||
| 権利 | ||||||
| 権利情報 | Copyright c 2005 IEEE. Reprinted from (relevant publication info). This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of Nagoya University’s products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. | |||||
| 言語 | en | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | Computer arithmetic | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | Euclidean norm | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | VLSI algorithm | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | digit-recurrence algorithm | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | computer graphics | |||||
| 抄録 | ||||||
| 内容記述タイプ | Abstract | |||||
| 内容記述 | A digit-recurrence algorithm for computing the Euclidean norm of a three-dimensional (3D) vector which often appears in 3D computer graphics is proposed. One of the three squarings required for the usual computation is removed and the other two squarings, as well as the two additions, are overlapped with the square rooting. The Euclidean norm is computed by iteration of carry-propagation-free additions, shifts, and multiplications by one digit. Different specific versions of the algorithm are possible, depending on the radix, the redundancy factor of the digit set, and etc. Each version of the algorithm can be implemented as a sequential (folded) circuit or a combinational (unfolded) circuit, which has a regular array structure suitable for VLSI. | |||||
| 言語 | en | |||||
| 出版者 | ||||||
| 出版者 | IEEE | |||||
| 言語 | en | |||||
| 言語 | ||||||
| 言語 | eng | |||||
| 資源タイプ | ||||||
| 資源タイプresource | http://purl.org/coar/resource_type/c_6501 | |||||
| タイプ | journal article | |||||
| 出版タイプ | ||||||
| 出版タイプ | VoR | |||||
| 出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||
| DOI | ||||||
| 関連タイプ | isVersionOf | |||||
| 識別子タイプ | DOI | |||||
| 関連識別子 | https://doi.org/10.1109/12.888043 | |||||
| ISSN | ||||||
| 収録物識別子タイプ | PISSN | |||||
| 収録物識別子 | 00189340 | |||||
| 書誌情報 |
en : IEEE Transactions on computers 巻 49, 号 10, p. 1074-1082, 発行日 2000-10 |
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| フォーマット | ||||||
| 値 | application/pdf | |||||
| 著者版フラグ | ||||||
| 値 | publisher | |||||
| URI | ||||||
| 識別子 | http://hdl.handle.net/2237/5291 | |||||
| 識別子タイプ | HDL | |||||
