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  1. A500 情報学部/情報学研究科・情報文化学部・情報科学研究科
  2. A500e 会議資料
  3. 国際会議

Energy Efficiency of Scratch-Pad Memory at 65 nm and Below: An Empirical Study

http://hdl.handle.net/2237/12084
http://hdl.handle.net/2237/12084
961e9f4c-ddfb-4789-a5e0-c105d93a317d
名前 / ファイル ライセンス アクション
icess2008.pdf icess2008.pdf (249.7 kB)
Item type 学術雑誌論文 / Journal Article(1)
公開日 2009-08-25
タイトル
タイトル Energy Efficiency of Scratch-Pad Memory at 65 nm and Below: An Empirical Study
言語 en
著者 Takase, Hideki

× Takase, Hideki

WEKO 31101

en Takase, Hideki

Search repository
Tomiyama, Hiroyuki

× Tomiyama, Hiroyuki

WEKO 31102

en Tomiyama, Hiroyuki

Search repository
Zeng, Gang

× Zeng, Gang

WEKO 31103

en Zeng, Gang

Search repository
Takada, Hiroaki

× Takada, Hiroaki

WEKO 31104

en Takada, Hiroaki

Search repository
アクセス権
アクセス権 open access
アクセス権URI http://purl.org/coar/access_right/c_abf2
権利
言語 en
権利情報 Copyright © 2008 IEEE. Reprinted from International Conference on Embedded Software and Systems, 2008. ICESS '08. p.93-97. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply <br/>IEEE endorsement of any of Nagoya University’s products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for <br/>creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org.
キーワード
主題Scheme Other
主題 Energy consumption
キーワード
主題Scheme Other
主題 scratch-pad memory
キーワード
主題Scheme Other
主題 embedded systems
キーワード
主題Scheme Other
主題 deep submicron
抄録
内容記述 A number of approaches have been proposed so far for reducing the energy consumption of embedded systems by using scratch-pad memory. However, most of previous work focused on dynamic energy reduction, and did not take enough consideration of the leakage energy in their evaluations. As the technology scales down to the deep submicron domain, the leakage energy in memory devices could contribute to a significant portion of the total energy consumption. Therefore, evaluation of energy consumption including the leakage energy is necessary. In this paper, we investigate the effectiveness of scratch-pad memory on energy reduction considering both the dynamic and leakage energy. The experiments are performed for 65 nm, 45 nm, and 32 nm technologies. The results demonstrate the effectiveness of scratch-pad memory in deep submicron technology. It is also observed that the leakage energy becomes less significant along with the technology scaling.
言語 en
内容記述タイプ Abstract
出版者
言語 en
出版者 IEEE
言語
言語 eng
資源タイプ
資源タイプresource http://purl.org/coar/resource_type/c_6501
タイプ journal article
出版タイプ
出版タイプ VoR
出版タイプResource http://purl.org/coar/version/c_970fb48d4fbd8a85
DOI
関連タイプ isVersionOf
識別子タイプ DOI
関連識別子 https://doi.org/10.1109/ICESS.2008.60
書誌情報 en : International Conference on Embedded Software and Systems (ICESS '08)

p. 93-97, 発行日 2008-07
フォーマット
application/pdf
著者版フラグ
値 publisher
URI
識別子 http://dx.doi.org/10.1109/ICESS.2008.60
識別子タイプ DOI
URI
識別子 http://hdl.handle.net/2237/12084
識別子タイプ HDL
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