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Energy Efficiency of Scratch-Pad Memory at 65 nm and Below: An Empirical Study
http://hdl.handle.net/2237/12084
961e9f4c-ddfb-4789-a5e0-c105d93a317d
名前 / ファイル | ライセンス | アクション | |
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Item type | 学術雑誌論文 / Journal Article(1) | |||||
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公開日 | 2009-08-25 | |||||
タイトル | ||||||
タイトル | Energy Efficiency of Scratch-Pad Memory at 65 nm and Below: An Empirical Study | |||||
著者 |
Takase, Hideki
× Takase, Hideki× Tomiyama, Hiroyuki× Zeng, Gang× Takada, Hiroaki |
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権利 | ||||||
権利情報 | Copyright © 2008 IEEE. Reprinted from International Conference on Embedded Software and Systems, 2008. ICESS '08. p.93-97. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of Nagoya University’s products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. |
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キーワード | ||||||
主題Scheme | Other | |||||
主題 | Energy consumption | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | scratch-pad memory | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | embedded systems | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | deep submicron | |||||
抄録 | ||||||
内容記述 | A number of approaches have been proposed so far for reducing the energy consumption of embedded systems by using scratch-pad memory. However, most of previous work focused on dynamic energy reduction, and did not take enough consideration of the leakage energy in their evaluations. As the technology scales down to the deep submicron domain, the leakage energy in memory devices could contribute to a significant portion of the total energy consumption. Therefore, evaluation of energy consumption including the leakage energy is necessary. In this paper, we investigate the effectiveness of scratch-pad memory on energy reduction considering both the dynamic and leakage energy. The experiments are performed for 65 nm, 45 nm, and 32 nm technologies. The results demonstrate the effectiveness of scratch-pad memory in deep submicron technology. It is also observed that the leakage energy becomes less significant along with the technology scaling. |
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内容記述タイプ | Abstract | |||||
出版者 | ||||||
出版者 | IEEE | |||||
言語 | ||||||
言語 | eng | |||||
資源タイプ | ||||||
資源タイプresource | http://purl.org/coar/resource_type/c_6501 | |||||
タイプ | journal article | |||||
書誌情報 |
International Conference on Embedded Software and Systems (ICESS '08) p. 93-97, 発行日 2008-07 |
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フォーマット | ||||||
application/pdf | ||||||
著者版フラグ | ||||||
値 | publisher | |||||
URI | ||||||
識別子 | http://dx.doi.org/10.1109/ICESS.2008.60 | |||||
識別子タイプ | DOI | |||||
URI | ||||||
識別子 | http://hdl.handle.net/2237/12084 | |||||
識別子タイプ | HDL |