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Energy-Efficient Pre-Execution Techniques in Two-Step Physical Register Deallocation
http://hdl.handle.net/2237/14940
http://hdl.handle.net/2237/14940d88e74ea-fe7b-405c-a36f-431b150004d4
名前 / ファイル | ライセンス | アクション |
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349.pdf (531.7 kB)
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Item type | 学術雑誌論文 / Journal Article(1) | |||||
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公開日 | 2011-06-24 | |||||
タイトル | ||||||
タイトル | Energy-Efficient Pre-Execution Techniques in Two-Step Physical Register Deallocation | |||||
言語 | en | |||||
著者 |
HYODO, Kazunaga
× HYODO, Kazunaga× IWAMOTO, Kengo× ANDO, Hideki |
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アクセス権 | ||||||
アクセス権 | open access | |||||
アクセス権URI | http://purl.org/coar/access_right/c_abf2 | |||||
権利 | ||||||
言語 | en | |||||
権利情報 | Copyright (C) 2009 IEICE | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | microarchitecture | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | microprocessor | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | instruction pre-execution | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | low power | |||||
抄録 | ||||||
内容記述 | Instruction pre-execution is an effective way to prefetch data. We previously proposed an instruction pre-execution scheme, which we call two-step physical register deallocation (TSD). The TSD realizes pre-execution by exploiting the difference between the amount of instruction-level parallelism available with an unlimited number of physical registers and that available with an actual number of physical registers. Although previous TSD study has successfully improved performance, it still has an inefficient energy consumption. This is because attempts are made for instructions to be pre-executed as much as possible, independently of whether or not they can significantly contribute to load latency reduction, allowing for maximal performance improvement. This paper presents a scheme that improves the energy efficiency of the TSD by pre-executing only those instructions that have great benefit. Our evaluation results using the SPECfp2000 benchmark show that our scheme reduces the dynamic pre-executed instruction count by 76%, compared with the original scheme. This reduction saves 7% energy consumption of the execution core with 2% overhead. Performance degrades by 2%, compared with that of the original scheme, but is still 15% higher than that of the normal processor without the TSD. | |||||
言語 | en | |||||
内容記述タイプ | Abstract | |||||
出版者 | ||||||
言語 | en | |||||
出版者 | Institute of Electronics, Information and Communication Engineers | |||||
言語 | ||||||
言語 | eng | |||||
資源タイプ | ||||||
資源タイプresource | http://purl.org/coar/resource_type/c_6501 | |||||
タイプ | journal article | |||||
出版タイプ | ||||||
出版タイプ | VoR | |||||
出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||
関連情報 | ||||||
関連タイプ | isVersionOf | |||||
識別子タイプ | URI | |||||
関連識別子 | http://www.ieice.org/jpn/trans_online/index.html | |||||
ISSN | ||||||
収録物識別子タイプ | PISSN | |||||
収録物識別子 | 0916-8532 | |||||
書誌情報 |
en : IEICE transactions on information and systems 巻 E92-D, 号 11, p. 2186-2195, 発行日 2009-11-01 |
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著者版フラグ | ||||||
値 | publisher | |||||
URI | ||||||
識別子 | http://www.ieice.org/jpn/trans_online/index.html | |||||
識別子タイプ | URI | |||||
URI | ||||||
識別子 | http://hdl.handle.net/2237/14940 | |||||
識別子タイプ | HDL |