WEKO3
アイテム
{"_buckets": {"deposit": "42992fe0-5e9d-49de-bfd5-c09a69fab689"}, "_deposit": {"id": "13172", "owners": [], "pid": {"revision_id": 0, "type": "depid", "value": "13172"}, "status": "published"}, "_oai": {"id": "oai:nagoya.repo.nii.ac.jp:00013172", "sets": ["322"]}, "author_link": ["41563", "41564", "41565"], "item_10_biblio_info_6": {"attribute_name": "書誌情報", "attribute_value_mlt": [{"bibliographicIssueDates": {"bibliographicIssueDate": "1997-10-20", "bibliographicIssueDateType": "Issued"}, "bibliographicIssueNumber": "10", "bibliographicPageEnd": "1882", "bibliographicPageStart": "1878", "bibliographicVolumeNumber": "E80-A", "bibliographic_titles": [{"bibliographic_title": "IEICE transactions on fundamentals of electronics, communications and computer sciences", "bibliographic_titleLang": "en"}]}]}, "item_10_description_4": {"attribute_name": "抄録", "attribute_value_mlt": [{"subitem_description": "In VLSI and printed wiring board design, routing process usually consists of two stages: the global routing and the detailed routing. The routability checking is to decide whether the global wires can be transformed into the detailed ones or not. In this paper, we propose two graphs, the capacity checking graph and the initial flow graph, for efficient routability checking in planar layouts.", "subitem_description_language": "en", "subitem_description_type": "Abstract"}]}, "item_10_identifier_60": {"attribute_name": "URI", "attribute_value_mlt": [{"subitem_identifier_type": "URI", "subitem_identifier_uri": "http://www.ieice.org/jpn/trans_online/index.html"}, {"subitem_identifier_type": "HDL", "subitem_identifier_uri": "http://hdl.handle.net/2237/15067"}]}, "item_10_publisher_32": {"attribute_name": "出版者", "attribute_value_mlt": [{"subitem_publisher": "Institute of Electronics, Information and Communication Engineers", "subitem_publisher_language": "en"}]}, "item_10_relation_43": {"attribute_name": "関連情報", "attribute_value_mlt": [{"subitem_relation_type": "isVersionOf", "subitem_relation_type_id": {"subitem_relation_type_id_text": "http://www.ieice.org/jpn/trans_online/index.html", "subitem_relation_type_select": "URI"}}]}, "item_10_rights_12": {"attribute_name": "権利", "attribute_value_mlt": [{"subitem_rights": "Copyright (C) 1997 IEICE", "subitem_rights_language": "en"}]}, "item_10_select_15": {"attribute_name": "著者版フラグ", "attribute_value_mlt": [{"subitem_select_item": "publisher"}]}, "item_10_source_id_7": {"attribute_name": "ISSN", "attribute_value_mlt": [{"subitem_source_identifier": "0916-8508", "subitem_source_identifier_type": "PISSN"}]}, "item_1615787544753": {"attribute_name": "出版タイプ", "attribute_value_mlt": [{"subitem_version_resource": "http://purl.org/coar/version/c_970fb48d4fbd8a85", "subitem_version_type": "VoR"}]}, "item_access_right": {"attribute_name": "アクセス権", "attribute_value_mlt": [{"subitem_access_right": "open access", "subitem_access_right_uri": "http://purl.org/coar/access_right/c_abf2"}]}, "item_creator": {"attribute_name": "著者", "attribute_type": "creator", "attribute_value_mlt": [{"creatorNames": [{"creatorName": "ISO, Naoyuki", "creatorNameLang": "en"}], "nameIdentifiers": [{"nameIdentifier": "41563", "nameIdentifierScheme": "WEKO"}]}, {"creatorNames": [{"creatorName": "KAWAGUCHI, Yasushi", "creatorNameLang": "en"}], "nameIdentifiers": [{"nameIdentifier": "41564", "nameIdentifierScheme": "WEKO"}]}, {"creatorNames": [{"creatorName": "HIRATA, Tomio", "creatorNameLang": "en"}], "nameIdentifiers": [{"nameIdentifier": "41565", "nameIdentifierScheme": "WEKO"}]}]}, "item_files": {"attribute_name": "ファイル情報", "attribute_type": "file", "attribute_value_mlt": [{"accessrole": "open_date", "date": [{"dateType": "Available", "dateValue": "2018-02-20"}], "displaytype": "detail", "download_preview_message": "", "file_order": 0, "filename": "466.pdf", "filesize": [{"value": "500.8 kB"}], "format": "application/pdf", "future_date_message": "", "is_thumbnail": false, "licensetype": "license_note", "mimetype": "application/pdf", "size": 500800.0, "url": {"label": "466.pdf", "objectType": "fulltext", "url": "https://nagoya.repo.nii.ac.jp/record/13172/files/466.pdf"}, "version_id": "0c4af479-a0d1-441b-8c24-312804b1ead3"}]}, "item_keyword": {"attribute_name": "キーワード", "attribute_value_mlt": [{"subitem_subject": "layout design", "subitem_subject_scheme": "Other"}, {"subitem_subject": "routability", "subitem_subject_scheme": "Other"}, {"subitem_subject": "routing", "subitem_subject_scheme": "Other"}]}, "item_language": {"attribute_name": "言語", "attribute_value_mlt": [{"subitem_language": "eng"}]}, "item_resource_type": {"attribute_name": "資源タイプ", "attribute_value_mlt": [{"resourcetype": "journal article", "resourceuri": "http://purl.org/coar/resource_type/c_6501"}]}, "item_title": "Efficient Routability Checking for Global Wires in Planar Layouts", "item_titles": {"attribute_name": "タイトル", "attribute_value_mlt": [{"subitem_title": "Efficient Routability Checking for Global Wires in Planar Layouts", "subitem_title_language": "en"}]}, "item_type_id": "10", "owner": "1", "path": ["322"], "permalink_uri": "http://hdl.handle.net/2237/15067", "pubdate": {"attribute_name": "PubDate", "attribute_value": "2011-07-13"}, "publish_date": "2011-07-13", "publish_status": "0", "recid": "13172", "relation": {}, "relation_version_is_last": true, "title": ["Efficient Routability Checking for Global Wires in Planar Layouts"], "weko_shared_id": -1}
Efficient Routability Checking for Global Wires in Planar Layouts
http://hdl.handle.net/2237/15067
http://hdl.handle.net/2237/15067e39f189a-c87a-47b8-9e7e-dd60d4dc67b6
名前 / ファイル | ライセンス | アクション |
---|---|---|
466.pdf (500.8 kB)
|
|
Item type | 学術雑誌論文 / Journal Article(1) | |||||
---|---|---|---|---|---|---|
公開日 | 2011-07-13 | |||||
タイトル | ||||||
タイトル | Efficient Routability Checking for Global Wires in Planar Layouts | |||||
言語 | en | |||||
著者 |
ISO, Naoyuki
× ISO, Naoyuki× KAWAGUCHI, Yasushi× HIRATA, Tomio |
|||||
アクセス権 | ||||||
アクセス権 | open access | |||||
アクセス権URI | http://purl.org/coar/access_right/c_abf2 | |||||
権利 | ||||||
言語 | en | |||||
権利情報 | Copyright (C) 1997 IEICE | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | layout design | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | routability | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | routing | |||||
抄録 | ||||||
内容記述 | In VLSI and printed wiring board design, routing process usually consists of two stages: the global routing and the detailed routing. The routability checking is to decide whether the global wires can be transformed into the detailed ones or not. In this paper, we propose two graphs, the capacity checking graph and the initial flow graph, for efficient routability checking in planar layouts. | |||||
言語 | en | |||||
内容記述タイプ | Abstract | |||||
出版者 | ||||||
言語 | en | |||||
出版者 | Institute of Electronics, Information and Communication Engineers | |||||
言語 | ||||||
言語 | eng | |||||
資源タイプ | ||||||
資源タイプresource | http://purl.org/coar/resource_type/c_6501 | |||||
タイプ | journal article | |||||
出版タイプ | ||||||
出版タイプ | VoR | |||||
出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||
関連情報 | ||||||
関連タイプ | isVersionOf | |||||
識別子タイプ | URI | |||||
関連識別子 | http://www.ieice.org/jpn/trans_online/index.html | |||||
ISSN | ||||||
収録物識別子タイプ | PISSN | |||||
収録物識別子 | 0916-8508 | |||||
書誌情報 |
en : IEICE transactions on fundamentals of electronics, communications and computer sciences 巻 E80-A, 号 10, p. 1878-1882, 発行日 1997-10-20 |
|||||
著者版フラグ | ||||||
値 | publisher | |||||
URI | ||||||
識別子 | http://www.ieice.org/jpn/trans_online/index.html | |||||
識別子タイプ | URI | |||||
URI | ||||||
識別子 | http://hdl.handle.net/2237/15067 | |||||
識別子タイプ | HDL |