| Item type |
itemtype_ver1(1) |
| 公開日 |
2022-05-11 |
| タイトル |
|
|
タイトル |
A Synthesis Method Based on Multi-Stage Optimization for Power-Efficient Integrated Optical Logic Circuits |
|
言語 |
en |
| 著者 |
MATSUO, Ryosuke
SHIOMI, Jun
ISHIHARA, Tohru
ONODERA, Hidetoshi
SHINYA, Akihiko
NOTOMI, Masaya
|
| アクセス権 |
|
|
アクセス権 |
open access |
|
アクセス権URI |
http://purl.org/coar/access_right/c_abf2 |
| 権利 |
|
|
言語 |
en |
|
権利情報 |
Copyright(C)2021 IEICE |
| キーワード |
|
|
主題Scheme |
Other |
|
主題 |
binary decision diagram |
| キーワード |
|
|
主題Scheme |
Other |
|
主題 |
logic circuit |
| キーワード |
|
|
主題Scheme |
Other |
|
主題 |
optical circuit |
| 内容記述 |
|
|
内容記述タイプ |
Abstract |
|
内容記述 |
Optical logic circuits based on integrated nanophotonics attract significant interest due to their ultra-high-speed operation. However, the power dissipation of conventional optical logic circuits is exponential to the number of inputs of target logic functions. This paper proposes a synthesis method reducing power dissipation to a polynomial order of the number of inputs while exploiting the high-speed nature. Our method divides the target logic function into multiple sub-functions with Optical-to-Electrical (OE) converters. Each sub-function has a smaller number of inputs than that of the original function, which enables to exponentially reduce the power dissipated by an optical logic circuit representing the sub-function. The proposed synthesis method can mitigate the OE converter delay overhead by parallelizing sub-functions. We apply the proposed synthesis method to the ISCAS'85 benchmark circuits. The power consumption of the conventional circuits based on the Binary Decision Diagram (BDD) is at least three orders of magnitude larger than that of the optical logic circuits synthesized by the proposed method. The proposed method reduces the power consumption to about 100mW. The delay of almost all the circuits synthesized by the proposed method is kept less than four times the delay of the conventional BDD-based circuit. |
|
言語 |
en |
| 出版者 |
|
|
出版者 |
電子情報通信学会 |
|
言語 |
ja |
| 言語 |
|
|
言語 |
eng |
| 資源タイプ |
|
|
資源タイプresource |
http://purl.org/coar/resource_type/c_6501 |
|
タイプ |
departmental bulletin paper |
| 出版タイプ |
|
|
出版タイプ |
VoR |
|
出版タイプResource |
http://purl.org/coar/version/c_970fb48d4fbd8a85 |
| 関連情報 |
|
|
関連タイプ |
isVersionOf |
|
|
識別子タイプ |
DOI |
|
|
関連識別子 |
https://doi.org/10.1587/transfun.2020KEP0018 |
| 収録物識別子 |
|
|
収録物識別子タイプ |
PISSN |
|
収録物識別子 |
0916-8508 |
| 書誌情報 |
en : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
巻 E104A,
号 11,
p. 1546-1554,
発行日 2021-11-01
|
| ファイル公開日 |
|
|
日付 |
2022-05-11 |
|
日付タイプ |
Available |
e104-a_11_1546.pdf (2.6 MB)
