| Item type |
itemtype_ver1(1) |
| 公開日 |
2022-05-13 |
| タイトル |
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|
タイトル |
Dynamic Verification of Approximate Computing Circuits using Coverage-based Grey-box Fuzzing |
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言語 |
en |
| 著者 |
Yoshisue, Kazuki
Masuda, Yutaka
Ishihara, Tohru
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| アクセス権 |
|
|
アクセス権 |
open access |
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アクセス権URI |
http://purl.org/coar/access_right/c_abf2 |
| 権利 |
|
|
言語 |
en |
|
権利情報 |
“© 2021 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes, creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.” |
| 内容記述 |
|
|
内容記述タイプ |
Abstract |
|
内容記述 |
Approximate computing (AC) has recently emerged as a promising approach to the energy-efficient design of digital systems. For realizing the practical AC design, we need to verify whether the designed circuit can operate correctly under various operating conditions. Namely, the verification needs to efficiently find fatal logic errors or timing errors that violate the constraint of computational quality. This paper proposes a novel dynamic verification methodology of the AC circuit. The key idea of the proposed methodology is to incorporate a quality assessment capability into the Coverage-based Grey-box Fuzzing (CGF). CGF is one of the most promising techniques in the research field of software security testing. By repeating (1) mutation of test patterns, (2) execution of the program under test (PUT), and (3) aggregation of coverage information and feedback to the next test pattern generation, CGF can explore the verification space quickly and automatically. On the other hand, CGF originally cannot consider the computational quality by itself. For overcoming this quality unawareness in CGF, the proposed methodology additionally embeds the Design Under Test (DUT) mechanisms into the calculation part of computational quality. Thanks to the integration of CGF and DUT mechanism, the proposed framework realizes the quality-aware feedback loop in CGF and thus quickly enhances the verification coverage for test patterns that violate the quality constraint. In this work, we quantitatively compared the verification coverage of the approximate arithmetic circuits between the proposed methodology and the random test. In a case study of an approximate multiply-accumulate (MAC) unit, we experimentally confirmed that the proposed methodology achieves the target coverage three times faster than the random test. |
|
言語 |
en |
| 内容記述 |
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内容記述タイプ |
Other |
|
内容記述 |
IOLTS 2021. June 28-30, 2021. Torino, Italy (Virtual) |
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言語 |
en |
| 出版者 |
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出版者 |
IEEE |
|
言語 |
en |
| 言語 |
|
|
言語 |
eng |
| 資源タイプ |
|
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資源タイプresource |
http://purl.org/coar/resource_type/c_5794 |
|
タイプ |
conference paper |
| 出版タイプ |
|
|
出版タイプ |
AM |
|
出版タイプResource |
http://purl.org/coar/version/c_ab4af688f83e57aa |
| 関連情報 |
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関連タイプ |
isVersionOf |
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|
識別子タイプ |
DOI |
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|
関連識別子 |
https://doi.org/10.1109/IOLTS52814.2021.9486690 |
| 関連情報 |
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関連タイプ |
isPartOf |
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|
識別子タイプ |
ISBN |
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|
関連識別子 |
978-1-6654-3371-6 |
| 収録物識別子 |
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収録物識別子タイプ |
PISSN |
|
収録物識別子 |
1942-9398 |
| 書誌情報 |
en : 2021 IEEE 27th International Symposium on On-Line Testing and Robust System Design (IOLTS)
p. 1-7,
発行日 2021-07
|
IOLTS_Yoshisue_submit.pdf (272 KB)
