| Item type |
itemtype_ver1(1) |
| 公開日 |
2023-03-06 |
| タイトル |
|
|
タイトル |
Dynamic Verification Framework of Approximate Computing Circuits using Quality-Aware Coverage-Based Grey-Box Fuzzing |
|
言語 |
en |
| 著者 |
MASUDA, Yutaka
HONDA, Yusei
ISHIHARA, Tohru
|
| アクセス権 |
|
|
アクセス権 |
open access |
|
アクセス権URI |
http://purl.org/coar/access_right/c_abf2 |
| 権利 |
|
|
言語 |
en |
|
権利情報 |
Copyright(C)2023 IEICE |
| キーワード |
|
|
主題Scheme |
Other |
|
主題 |
approximate computing (AC) |
| キーワード |
|
|
主題Scheme |
Other |
|
主題 |
coverage-based grey-box fuzzing (CGF) |
| キーワード |
|
|
主題Scheme |
Other |
|
主題 |
design under verification (DUV) integration |
| キーワード |
|
|
主題Scheme |
Other |
|
主題 |
verification |
| キーワード |
|
|
主題Scheme |
Other |
|
主題 |
computational quality |
| 内容記述 |
|
|
内容記述タイプ |
Abstract |
|
内容記述 |
Approximate computing (AC) has recently emerged as a promising approach to the energy-efficient design of digital systems. For realizing the practical AC design, we need to verify whether the designed circuit can operate correctly under various operating conditions. Namely, the verification needs to efficiently find fatal logic errors or timing errors that violate the constraint of computational quality. This work focuses on the verification where the computational results can be observed, the computational quality can be calculated from computational results, and the constraint of computational quality is given and defined as the constraint which is set to the computational quality of designed AC circuit with given workloads. Then, this paper proposes a novel dynamic verification framework of the AC circuit. The key idea of the proposed framework is to incorporate a quality assessment capability into the Coverage-based Grey-box Fuzzing (CGF). CGF is one of the most promising techniques in the research field of software security testing. By repeating (1) mutation of test patterns, (2) execution of the program under test (PUT), and (3) aggregation of coverage information and feedback to the next test pattern generation, CGF can explore the verification space quickly and automatically. On the other hand, CGF originally cannot consider the computational quality by itself. For overcoming this quality unawareness in CGF, the proposed framework additionally embeds the Design Under Verification (DUV) component into the calculation part of computational quality. Thanks to the DUV integration, the proposed framework realizes the quality-aware feedback loop in CGF and thus quickly enhances the verification coverage for test patterns that violate the quality constraint. In this work, we quantitatively compared the verification coverage of the approximate arithmetic circuits between the proposed framework and the random test. In a case study of an approximate multiply-accumulate (MAC) unit, we experimentally confirmed that the proposed framework achieved 3.85 to 10.36 times higher coverage than the random test. |
|
言語 |
en |
| 出版者 |
|
|
出版者 |
電子情報通信学会 |
|
言語 |
ja |
| 言語 |
|
|
言語 |
eng |
| 資源タイプ |
|
|
資源タイプ識別子 |
http://purl.org/coar/resource_type/c_6501 |
|
資源タイプ |
journal article |
| 出版タイプ |
|
|
出版タイプ |
VoR |
|
出版タイプResource |
http://purl.org/coar/version/c_970fb48d4fbd8a85 |
| 関連情報 |
|
|
関連タイプ |
isVersionOf |
|
|
識別子タイプ |
DOI |
|
|
関連識別子 |
https://doi.org/10.1587/transfun.2022VLP0002 |
| 収録物識別子 |
|
|
収録物識別子タイプ |
PISSN |
|
収録物識別子 |
0916-8508 |
| 書誌情報 |
en : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
巻 E106A,
号 3,
p. 514-522,
発行日 2023-03-01
|
Masuda_IEICE.pdf (2.2 MB)
