| Item type |
itemtype_ver1(1) |
| 公開日 |
2023-03-06 |
| タイトル |
|
|
タイトル |
An Accuracy Reconfigurable Vector Accelerator based on Approximate Logarithmic Multipliers for Energy-Efficient Computing |
|
言語 |
en |
| 著者 |
HOU, Lingxiao
MASUDA, Yutaka
ISHIHARA, Tohru
|
| アクセス権 |
|
|
アクセス権 |
open access |
|
アクセス権URI |
http://purl.org/coar/access_right/c_abf2 |
| 権利 |
|
|
言語 |
en |
|
権利情報 |
Copyright(C)2023 IEICE |
| キーワード |
|
|
主題Scheme |
Other |
|
主題 |
approximate computing |
| キーワード |
|
|
主題Scheme |
Other |
|
主題 |
energy-efficient computing |
| キーワード |
|
|
主題Scheme |
Other |
|
主題 |
low power design |
| キーワード |
|
|
主題Scheme |
Other |
|
主題 |
vector acceleration |
| キーワード |
|
|
主題Scheme |
Other |
|
主題 |
single instruction multiple data |
| 内容記述 |
|
|
内容記述タイプ |
Abstract |
|
内容記述 |
The approximate logarithmic multiplier proposed by Mitchell provides an efficient alternative for processing dense multiplication or multiply-accumulate operations in applications such as image processing and real-time robotics. It offers the advantages of small area, high energy efficiency and is suitable for applications that do not necessarily achieve high accuracy. However, its maximum error of 11.1% makes it challenging to deploy in applications requiring relatively high accuracy. This paper proposes a novel operand decomposition method (OD) that decomposes one multiplication into the sum of multiple approximate logarithmic multiplications to widely reduce Mitchell multiplier errors while taking full advantage of its area savings. Based on the proposed OD method, this paper also proposes an accuracy reconfigurable multiply-accumulate (MAC) unit that provides multiple reconfigurable accuracies with high parallelism. Compared to a MAC unit consisting of accurate multipliers, the area is significantly reduced to less than half, improving the hardware parallelism while satisfying the required accuracy for various scenarios. The experimental results show the excellent applicability of our proposed MAC unit in image smoothing and robot localization and mapping application. We have also designed a prototype processor that integrates the minimum functionality of this MAC unit as a vector accelerator and have implemented a software-level accuracy reconfiguration in the form of an instruction set extension. We experimentally confirmed the correct operation of the proposed vector accelerator, which provides the different degrees of accuracy and parallelism at the software level. |
|
言語 |
en |
| 出版者 |
|
|
出版者 |
電子情報通信学会 |
|
言語 |
ja |
| 言語 |
|
|
言語 |
eng |
| 資源タイプ |
|
|
資源タイプresource |
http://purl.org/coar/resource_type/c_6501 |
|
タイプ |
journal article |
| 出版タイプ |
|
|
出版タイプ |
VoR |
|
出版タイプResource |
http://purl.org/coar/version/c_970fb48d4fbd8a85 |
| 関連情報 |
|
|
関連タイプ |
isVersionOf |
|
|
識別子タイプ |
DOI |
|
|
関連識別子 |
https://doi.org/10.1587/transfun.2022VLP0005 |
| 収録物識別子 |
|
|
収録物識別子タイプ |
PISSN |
|
収録物識別子 |
0916-8508 |
| 書誌情報 |
en : IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
巻 E106A,
号 3,
p. 532-541,
発行日 2023-03-01
|
Hou_IEICE.pdf (5.6 MB)
