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単一磁束量子デバイスを用いた次世代プロセッサのマイクロアーキテクチャ探索
http://hdl.handle.net/2237/23812
http://hdl.handle.net/2237/238129f7f8a8c-88bf-41ec-89a2-470f9c82e3a1
名前 / ファイル | ライセンス | アクション |
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110009889371.pdf (1.0 MB)
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Item type | 学術雑誌論文 / Journal Article(1) | |||||
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公開日 | 2016-03-14 | |||||
タイトル | ||||||
タイトル | 単一磁束量子デバイスを用いた次世代プロセッサのマイクロアーキテクチャ探索 | |||||
言語 | ja | |||||
その他のタイトル | ||||||
その他のタイトル | Exploring Microarchitecture for Next Generation Single-Flux-Quantum Processors | |||||
言語 | en | |||||
著者 |
横田, 順平
× 横田, 順平× 津秦, 伴紀× 井上, 弘士× 田中, 雅光× YOKOTA, Jumpei× TSUHATA, Tomonori× INOUE, Koji× TANAKA, Masami |
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アクセス権 | ||||||
アクセス権 | open access | |||||
アクセス権URI | http://purl.org/coar/access_right/c_abf2 | |||||
権利 | ||||||
言語 | ja | |||||
権利情報 | (c)一般社団法人電子情報通信学会 本文データは学協会の許諾に基づきCiNiiから複製したものである | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | SFQ回路 | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | マイクロプロセッサ | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | アーキテクチャ | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | 性能モデリング | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | SFQ | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | Microprocessor | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | Architectuire | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | Performance Modeling | |||||
抄録 | ||||||
内容記述 | 単一磁束量子(Single-Flux-Quantum;SFQ)マイクロプロセッサは,超伝導体素子によって構成され,極めて低消費電力で動作する次世代プロセッサである.デバイスの特性上,CMOSプロセッサと異なる新たなパイプライン構成およびビット幅の設計空間が考えられる.そこで,本稿ではSFQマイクロプロセッサの性能モデリングを行い,モデルに基づくマイクロアーキテクチャ探索を行う. | |||||
言語 | ja | |||||
内容記述タイプ | Abstract | |||||
抄録 | ||||||
内容記述 | Single-Flux-Quantum (SFQ) is a promising device technology to implement high-performance low-power microprocessors. Since it operates at the superconductive condition, the negative impact of resistance can dramatically reduced. Previous design of a SFQ microprocessor employs a bit-serial implementation for instruction pipelining. However, since there is a trade-off between bit-level parallelism and operation frequency, it is still not clear that this kind of bit-level operation is suitable for SFQ microprocessors. To answer this question, this paper explore the SFQ pipeline micro-architecture and evaluates their performance. | |||||
言語 | en | |||||
内容記述タイプ | Abstract | |||||
内容記述 | ||||||
内容記述 | IEICE Technical Report;CPM2013-115, IEICE Technical Report;ICD2013-92 | |||||
言語 | en | |||||
内容記述タイプ | Other | |||||
出版者 | ||||||
言語 | ja | |||||
出版者 | 一般社団法人電子情報通信学会 | |||||
言語 | ||||||
言語 | jpn | |||||
資源タイプ | ||||||
資源タイプresource | http://purl.org/coar/resource_type/c_6501 | |||||
タイプ | journal article | |||||
出版タイプ | ||||||
出版タイプ | VoR | |||||
出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||
関連情報 | ||||||
関連タイプ | isVersionOf | |||||
識別子タイプ | URI | |||||
関連識別子 | http://ci.nii.ac.jp/naid/110009889371/ | |||||
ISSN | ||||||
収録物識別子タイプ | PISSN | |||||
収録物識別子 | 0913-5685 | |||||
書誌情報 |
ja : 電子情報通信学会技術研究報告. ICD, 集積回路 巻 113, 号 323, p. 43-48, 発行日 2013-11 |
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著者版フラグ | ||||||
値 | publisher | |||||
シリーズ | ||||||
関連名称 | IEICE Technical Report;CPM2013-115 | |||||
シリーズ | ||||||
関連名称 | IEICE Technical Report;ICD2013-92 | |||||
URI | ||||||
識別子 | http://ci.nii.ac.jp/naid/110009889371/ | |||||
識別子タイプ | URI | |||||
URI | ||||||
識別子 | http://hdl.handle.net/2237/23812 | |||||
識別子タイプ | HDL |