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Impossibility of Classically Simulating One-Clean-Qubit Model with Multiplicative Error
http://hdl.handle.net/2237/00028747
http://hdl.handle.net/2237/000287470c641f00-5708-49b0-82cf-bada43d526e2
名前 / ファイル | ライセンス | アクション |
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PhysRevLett120_200502 (201.0 kB)
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Item type | 学術雑誌論文 / Journal Article(1) | |||||
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公開日 | 2018-11-01 | |||||
タイトル | ||||||
タイトル | Impossibility of Classically Simulating One-Clean-Qubit Model with Multiplicative Error | |||||
言語 | en | |||||
著者 |
Fujii, Keisuke
× Fujii, Keisuke× Kobayashi, Hirotada× Morimae, Tomoyuki× Nishimura, Harumichi× Tamate, Shuhei× Tani, Seiichiro |
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アクセス権 | ||||||
アクセス権 | open access | |||||
アクセス権URI | http://purl.org/coar/access_right/c_abf2 | |||||
権利 | ||||||
言語 | en | |||||
権利情報 | © 2018 American Physical Society | |||||
抄録 | ||||||
内容記述 | The one-clean-qubit model (or the deterministic quantum computation with one quantum bit model) is a restricted model of quantum computing where all but a single input qubits are maximally mixed. It is known that the probability distribution of measurement results on three output qubits of the one-clean-qubit model cannot be classically efficiently sampled within a constant multiplicative error unless the polynomial-time hierarchy collapses to the third level [T. Morimae, K. Fujii, and J. F. Fitzsimons, Phys. Rev. Lett. 112, 130502 (2014)]. It was open whether we can keep the no-go result while reducing the number of output qubits from three to one. Here, we solve the open problem affirmatively. We also show that the third-level collapse of the polynomial-time hierarchy can be strengthened to the second-level one. The strengthening of the collapse level from the third to the second also holds for other subuniversal models such as the instantaneous quantum polynomial model [M. Bremner, R. Jozsa, and D. J. Shepherd, Proc. R. Soc. A 467, 459 (2011)] and the boson sampling model [S. Aaronson and A. Arkhipov, STOC 2011, p. 333]. We additionally study the classical simulatability of the one-clean-qubit model with further restrictions on the circuit depth or the gate types. | |||||
言語 | en | |||||
内容記述タイプ | Abstract | |||||
出版者 | ||||||
言語 | en | |||||
出版者 | American Physical Society | |||||
言語 | ||||||
言語 | eng | |||||
資源タイプ | ||||||
資源タイプresource | http://purl.org/coar/resource_type/c_6501 | |||||
タイプ | journal article | |||||
出版タイプ | ||||||
出版タイプ | VoR | |||||
出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||
DOI | ||||||
関連タイプ | isVersionOf | |||||
識別子タイプ | DOI | |||||
関連識別子 | https://doi.org/10.1103/PhysRevLett.120.200502 | |||||
ISSN(print) | ||||||
収録物識別子タイプ | PISSN | |||||
収録物識別子 | 0031-9007 | |||||
ISSN(Online) | ||||||
収録物識別子タイプ | EISSN | |||||
収録物識別子 | 1079-7114 | |||||
書誌情報 |
en : Physical Review Letters 巻 120, 号 20, p. 200502, 発行日 2018-05-17 |
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著者版フラグ | ||||||
値 | publisher |