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  1. A500 情報学部/情報学研究科・情報文化学部・情報科学研究科
  2. A500a 雑誌掲載論文
  3. 学術雑誌

MTTF-Aware Design Methodology of Adaptively Voltage Scaled Circuit with Timing Error Predictive Flip-Flop

http://hdl.handle.net/2237/00030805
7d5f36e5-75e9-462e-808f-15bf8a857bc9
名前 / ファイル ライセンス アクション
e102-a_7_867.pdf e102-a_7_867 (1.2 MB)
Item type 学術雑誌論文 / Journal Article(1)
公開日 2019-10-15
タイトル
タイトル MTTF-Aware Design Methodology of Adaptively Voltage Scaled Circuit with Timing Error Predictive Flip-Flop
著者 MASUDA, Yutaka

× MASUDA, Yutaka

WEKO 93691

MASUDA, Yutaka

Search repository
HASHIMOTO, Masanori

× HASHIMOTO, Masanori

WEKO 93692

HASHIMOTO, Masanori

Search repository
権利
権利情報 copyright©2019 IEICE
キーワード
主題Scheme Other
主題 adaptive voltage scaling
キーワード
主題Scheme Other
主題 activation-aware slack assignment
キーワード
主題Scheme Other
主題 mean time to failure
キーワード
主題Scheme Other
主題 timing error predictive FF
抄録
内容記述 Adaptive voltage scaling is a promising approach to overcome manufacturing variability, dynamic environmental fluctuation, and aging. This paper focuses on error prediction based adaptive voltage scaling (EP-AVS) and proposes a mean time to failure (MTTF) aware design methodology for EP-AVS circuits. Main contributions of this work include (1) optimization of both voltage-scaled circuit and voltage control logic, and (2) quantitative evaluation of power saving for practically long MTTF. Experimental results show that the proposed EP-AVS design methodology achieves 38.0% power saving while satisfying given target MTTF.
内容記述タイプ Abstract
出版者
出版者 一般社団法人 電子情報通信学会
言語
言語 eng
資源タイプ
資源タイプresource http://purl.org/coar/resource_type/c_6501
タイプ journal article
DOI
関連識別子
識別子タイプ DOI
関連識別子 https://doi.org/10.1587/transfun.E102.A.867
ISSN(print)
収録物識別子タイプ ISSN
収録物識別子 0916-8508
書誌情報 IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences

巻 102, 号 7, p. 867-877, 発行日 2019-07
著者版フラグ
値 publisher
関係URI
関連名称
関連名称 http://www.ieice.org/jpn/books/transaction.html
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