{"_buckets": {"deposit": "6b6a0bbf-ad2a-41ad-9e5e-05ff4478aaaf"}, "_deposit": {"id": "3865", "owners": [], "pid": {"revision_id": 0, "type": "depid", "value": "3865"}, "status": "published"}, "_oai": {"id": "oai:nagoya.repo.nii.ac.jp:00003865"}, "item_10_biblio_info_6": {"attribute_name": "\u66f8\u8a8c\u60c5\u5831", "attribute_value_mlt": [{"bibliographicIssueDates": {"bibliographicIssueDate": "1999-01", "bibliographicIssueDateType": "Issued"}, "bibliographicIssueNumber": "1", "bibliographicPageEnd": "80", "bibliographicPageStart": "76", "bibliographicVolumeNumber": "48", "bibliographic_titles": [{"bibliographic_title": "IEEE Transactions on computers"}]}]}, "item_10_description_4": {"attribute_name": "\u6284\u9332", "attribute_value_mlt": [{"subitem_description": "An efficient parallel adder under left-to-right input arrival is proposed. Making full use of the delay of the input arrival, it produces the sum within a small constant delay after the arrival of the final bits. Its amount of hardware is proportional to the operand length. It can be applied to the quotient conversion in an array divider.", "subitem_description_type": "Abstract"}]}, "item_10_identifier_60": {"attribute_name": "URI", "attribute_value_mlt": [{"subitem_identifier_type": "HDL", "subitem_identifier_uri": "http://hdl.handle.net/2237/5290"}]}, "item_10_publisher_32": {"attribute_name": "\u51fa\u7248\u8005", "attribute_value_mlt": [{"subitem_publisher": "IEEE"}]}, "item_10_relation_11": {"attribute_name": "DOI", "attribute_value_mlt": [{"subitem_relation_type_id": {"subitem_relation_type_id_text": "http://doi.org/10.1109/12.743413", "subitem_relation_type_select": "DOI"}}]}, "item_10_rights_12": {"attribute_name": "\u6a29\u5229", "attribute_value_mlt": [{"subitem_rights": "Copyright c 2005 IEEE. Reprinted from (relevant publication info). This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of Nagoya University\u2019s products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org."}]}, "item_10_select_15": {"attribute_name": "\u8457\u8005\u7248\u30d5\u30e9\u30b0", "attribute_value_mlt": [{"subitem_select_item": "publisher"}]}, "item_10_source_id_7": {"attribute_name": "ISSN", "attribute_value_mlt": [{"subitem_source_identifier": "00189340", "subitem_source_identifier_type": "ISSN"}]}, "item_10_text_14": {"attribute_name": "\u30d5\u30a9\u30fc\u30de\u30c3\u30c8", "attribute_value_mlt": [{"subitem_text_value": "application/pdf"}]}, "item_creator": {"attribute_name": "\u8457\u8005", "attribute_type": "creator", "attribute_value_mlt": [{"creatorNames": [{"creatorName": "\u9ad8\u6728, \u76f4\u53f2"}], "nameIdentifiers": [{"nameIdentifier": "9760", "nameIdentifierScheme": "WEKO"}]}, {"creatorNames": [{"creatorName": "Takagi, Naofumi"}], "nameIdentifiers": [{"nameIdentifier": "9761", "nameIdentifierScheme": "WEKO"}]}]}, "item_files": {"attribute_name": "\u30d5\u30a1\u30a4\u30eb\u60c5\u5831", "attribute_type": "file", "attribute_value_mlt": [{"accessrole": "open_date", "date": [{"dateType": "Available", "dateValue": "2018-02-19"}], "displaytype": "detail", "download_preview_message": "", "file_order": 0, "filename": "00743413.pdf", "filesize": [{"value": "251.8 kB"}], "format": "application/pdf", "future_date_message": "", "is_thumbnail": false, "licensetype": "license_free", "mimetype": "application/pdf", "size": 251800.0, "url": {"label": "00743413.pdf", "url": "https://nagoya.repo.nii.ac.jp/record/3865/files/00743413.pdf"}, "version_id": "c75a1988-4107-4fb0-8671-fc896c5fb0a7"}]}, "item_keyword": {"attribute_name": "\u30ad\u30fc\u30ef\u30fc\u30c9", "attribute_value_mlt": [{"subitem_subject": "Arithmetic circuit", "subitem_subject_scheme": "Other"}, {"subitem_subject": "adder", "subitem_subject_scheme": "Other"}, {"subitem_subject": "on-the-fly conversion", "subitem_subject_scheme": "Other"}, {"subitem_subject": "divider", "subitem_subject_scheme": "Other"}]}, "item_language": {"attribute_name": "\u8a00\u8a9e", "attribute_value_mlt": [{"subitem_language": "eng"}]}, "item_resource_type": {"attribute_name": "\u8cc7\u6e90\u30bf\u30a4\u30d7", "attribute_value_mlt": [{"resourcetype": "journal article", "resourceuri": "http://purl.org/coar/resource_type/c_6501"}]}, "item_title": "A high-speed reduced-size adder under left-to-right input arrival", "item_titles": {"attribute_name": "\u30bf\u30a4\u30c8\u30eb", "attribute_value_mlt": [{"subitem_title": "A high-speed reduced-size adder under left-to-right input arrival"}]}, "item_type_id": "10", "owner": "1", "path": ["312/313/314"], "permalink_uri": "http://hdl.handle.net/2237/5290", "pubdate": {"attribute_name": "\u516c\u958b\u65e5", "attribute_name_i18n": "\u516c\u958b\u65e5", "attribute_value": "2006-01-10"}, "publish_date": "2006-01-10", "publish_status": "0", "recid": "3865", "relation": {}, "relation_version_is_last": true, "title": ["A high-speed reduced-size adder under left-to-right input arrival"], "weko_shared_id": 3}