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In SFQ digital circuits, unlike CMOS digital circuits, a pulse is used as a carrier of information and the representation of the logic values is different from that in CMOS digital circuits. Therefore, design automation algorithms and structure of arithmetic circuits suitable for SFQ digital circuits are different from those for CMOS digital circuits. In addition, design of SFQ circuits has been carried out largely manually. For advancing studies of SFQ digital circuits, design automation algorithms which can design highperformance SFQ circuits are important. Furthermore, studies of circuit structure suitable for SFQ arithmetic circuits are also important for designing highperformance circuits. In this dissertation, several design automation algorithms and design of a multiplier which is one of the most important arithmetic circuits are proposed for SFQ digital circuits. In Chapter 1, the background and the outline of the dissertation are described. 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The experimental results on benchmark circuits show that the proposed method synthesizes dualrail SFQ digital circuits that consist of about 27.1% fewer logic elements than those synthesized by a Transductionbased method on average. In Chapter 4, an algorithm for clock scheduling of synchronous clocking SFQ digital circuits is proposed. In synchronous clocking SFQ digital circuits, all logic gates are driven by clock pulses. Appropriate clock scheduling makes clock frequency of the circuits higher. Given a clock period, the proposed algorithm determines the arrival time of clock pulses of each gate and the delay that should be inserted. The experimental results on benchmark circuits show that inserted delay elements by the proposed algorithm are 59.0% fewer and the height of clock trees are 40.4% shorter on average than those by a straightforward algorithm. The proposed algorithm can also be used to minimize the clock period, thus obtaining 19.0% shorter clock periods on average. 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The experimental results on benchmark circuits show that compared with a conventional method for CMOS digital circuits, the proposed method synthesizes circuits that work with 4.9 times higher clock frequency and have 17.3% more gates on average. In Chapter 6, an integer multiplier with systolic array structure is proposed for syn chronous clocking SFQ digital circuits. The systolic array is a circuit structure for VLSIs and consists of regularly arranged simple processing elements (PEs). For evaluating the proposed multiplier, a 4bit systolic multiplier and a 4bit array multiplier which is one of the most typical parallel multipliers are designed and compared with each other. The results of the design and a digital simulation show that the circuit area of the 4bit systolic multiplier is almost the half of that of the 4bit array multiplier, and the latency is about 1.5 times longer. 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Studies on Design Automation and Arithmetic Circuit Design for SingleFluxQuantum Digital Circuits
http://hdl.handle.net/2237/10343
f0fba915354a43c4aaa6a871e26bfe97
名前 / ファイル  ライセンス  アクション  

obata_doctor_thesis.pdf (840.6 kB)


Item type  学位論文 / Thesis or Dissertation(1)  

公開日  20080811  
タイトル  
タイトル  Studies on Design Automation and Arithmetic Circuit Design for SingleFluxQuantum Digital Circuits  
著者 
小畑, 幸嗣
× 小畑, 幸嗣× Obata, Koji 

抄録  
内容記述タイプ  Abstract  
内容記述  Superconductive singlefluxquantum (SFQ) circuit technology attracts attention as a next generation technology of integrated circuits because of its ultrafast computation speed and low power consumption. In SFQ digital circuits, unlike CMOS digital circuits, a pulse is used as a carrier of information and the representation of the logic values is different from that in CMOS digital circuits. Therefore, design automation algorithms and structure of arithmetic circuits suitable for SFQ digital circuits are different from those for CMOS digital circuits. In addition, design of SFQ circuits has been carried out largely manually. For advancing studies of SFQ digital circuits, design automation algorithms which can design highperformance SFQ circuits are important. Furthermore, studies of circuit structure suitable for SFQ arithmetic circuits are also important for designing highperformance circuits. In this dissertation, several design automation algorithms and design of a multiplier which is one of the most important arithmetic circuits are proposed for SFQ digital circuits. In Chapter 1, the background and the outline of the dissertation are described. In Chapter 2, the basis of SFQ circuits and the representation of logic values for SFQ digital circuits are described. There are two methods of representation of the logic values. One is ‘dualrail representation’ in which “1” and “0” lines are used and the other is ‘synchronous clocking representation’ in which synchronizing clocks are used. In Chapter 3, a new method of logic synthesis for dualrail SFQ digital circuits are pro posed. For representing logic functions, a rootshared binary decision diagram (RSBDD) which is a directed acyclic graph constructed from binary decision diagrams is proposed. In the method, first an RSBDD is constructed from given logic functions, and then the number of nodes in the constructed RSBDD is reduced by variable reordering. Finally, a dualrail SFQ digital circuit is synthesized from the reduced RSBDD. The experimental results on benchmark circuits show that the proposed method synthesizes dualrail SFQ digital circuits that consist of about 27.1% fewer logic elements than those synthesized by a Transductionbased method on average. In Chapter 4, an algorithm for clock scheduling of synchronous clocking SFQ digital circuits is proposed. In synchronous clocking SFQ digital circuits, all logic gates are driven by clock pulses. Appropriate clock scheduling makes clock frequency of the circuits higher. Given a clock period, the proposed algorithm determines the arrival time of clock pulses of each gate and the delay that should be inserted. The experimental results on benchmark circuits show that inserted delay elements by the proposed algorithm are 59.0% fewer and the height of clock trees are 40.4% shorter on average than those by a straightforward algorithm. The proposed algorithm can also be used to minimize the clock period, thus obtaining 19.0% shorter clock periods on average. In Chapter 5, a synthesis method of sequential circuits is proposed for synchronous clocking SFQ digital circuits. Since all logic gates of synchronous clocking SFQ digital circuits are driven by a clock signal, synthesis methods of sequential circuits for CMOS digital circuits cannot derive the full power of highthroughput computation of SFQ circuit technology. In the method, a ‘state module’ consisting of a D flipflop (DFF) and several AND gates is used. First, states of a sequential machine are encoded by onehot encoding and state modules are assigned to the states one by one, and then, the modules are connected with each other according to the state transition. For the connection, confluence buffers (CBs), i.e., merger gates without clock signals are used. Consequently, gates driven by a clock signal are removed from its feedback loops, and therefore, a high throughput SFQ sequential circuit is achieved. The experimental results on benchmark circuits show that compared with a conventional method for CMOS digital circuits, the proposed method synthesizes circuits that work with 4.9 times higher clock frequency and have 17.3% more gates on average. In Chapter 6, an integer multiplier with systolic array structure is proposed for syn chronous clocking SFQ digital circuits. The systolic array is a circuit structure for VLSIs and consists of regularly arranged simple processing elements (PEs). For evaluating the proposed multiplier, a 4bit systolic multiplier and a 4bit array multiplier which is one of the most typical parallel multipliers are designed and compared with each other. The results of the design and a digital simulation show that the circuit area of the 4bit systolic multiplier is almost the half of that of the 4bit array multiplier, and the latency is about 1.5 times longer. Our estimation of the performance of larger scale multipliers shows that the proposed systolic multiplier achieves comparable latency to the array multiplier with extremely smaller circuit area when the bitwidth of input is large. A 1bit PE of the systolic multiplier is fabricated using NEC standard Nb process and successfully tested at low speed. In Chapter 7, conclusion and future works are stated. The knowledge obtained through the design automation algorithms will be bases of the development of computeraided design (CAD) systems for SFQ digital circuits. The result obtained through the study of the systolic multiplier is valuable knowledge for designing SFQ arithmetic circuits. Development of SFQspecific algorithms and methods makes the performance of SFQ digital circuits higher.  
内容記述  
内容記述タイプ  Other  
内容記述  名古屋大学博士学位論文 学位の種類:博士(情報科学) 学位授与年月日:平成20年3月25日  
言語  
言語  eng  
資源タイプ  
資源  http://purl.org/coar/resource_type/c_46ec  
タイプ  thesis  
書誌情報  発行日 20080325  
学位授与年度  
学位授与年度  2007  
学位授与年月日  
学位授与年月日  20080325  
学位授与番号  
学位授与番号  13901甲第8025号  
フォーマット  
application/pdf  
著者版フラグ  
値  publisher  
URI  
識別子  http://hdl.handle.net/2237/10343  
識別子タイプ  HDL 