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Hierarchical scheduling for integrating real-time applications with interrupt routines
http://hdl.handle.net/2237/13890
http://hdl.handle.net/2237/138902aabece9-c706-4389-a1ed-87a2769b7c4c
名前 / ファイル | ライセンス | アクション |
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matsubara.pdf (253.3 kB)
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Item type | 学術雑誌論文 / Journal Article(1) | |||||
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公開日 | 2010-07-30 | |||||
タイトル | ||||||
タイトル | Hierarchical scheduling for integrating real-time applications with interrupt routines | |||||
言語 | en | |||||
著者 |
Matsubara, Yutaka
× Matsubara, Yutaka× Honda, Shinya× Takada, Hiroaki |
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アクセス権 | ||||||
アクセス権 | open access | |||||
アクセス権URI | http://purl.org/coar/access_right/c_abf2 | |||||
権利 | ||||||
言語 | en | |||||
権利情報 | ©2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. | |||||
抄録 | ||||||
内容記述 | This paper presents a split interrupt routine model for a two-level hierarchical scheduling in order to integrate multiple independently developed applications that consist of tasks and interrupt routines into a shared CPU. In this model, an interrupt routine is split into an Interrupt Handler (IH), providing device-depended service, and an Interrupt Service Task (IST), providing application-specific service. By using this model, a main part of an interrupt routine is handled as a task and become controllable by global EDF scheduling. We implement this model on an actual processor to evaluate the response time and overhead of activating an IST. Furthermore, we analyze the schedulability of the applications including delay caused by interrupt disabled time and propose a simple schedulability test method. This method helps system integrators, such as automotive manufacturers, to quickly determine which applications could be integrated to the system without detail knowledge of each application in the system design phase. | |||||
言語 | en | |||||
内容記述タイプ | Abstract | |||||
出版者 | ||||||
言語 | en | |||||
出版者 | IEEE | |||||
言語 | ||||||
言語 | eng | |||||
資源タイプ | ||||||
資源タイプresource | http://purl.org/coar/resource_type/c_6501 | |||||
タイプ | journal article | |||||
出版タイプ | ||||||
出版タイプ | VoR | |||||
出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||
DOI | ||||||
関連タイプ | isVersionOf | |||||
識別子タイプ | DOI | |||||
関連識別子 | https://doi.org/10.1109/SOCDC.2009.5423838 | |||||
ISBN | ||||||
関連タイプ | isPartOf | |||||
識別子タイプ | ISBN | |||||
関連識別子 | 978-1-4244-5034-3 | |||||
書誌情報 |
en : 2009 International SoC Design Conference (ISOCC) p. 384-387, 発行日 2009-09-22 |
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フォーマット | ||||||
application/pdf | ||||||
著者版フラグ | ||||||
値 | publisher | |||||
URI | ||||||
識別子 | http://hdl.handle.net/2237/13890 | |||||
識別子タイプ | HDL | |||||
URI | ||||||
識別子 | http://dx.doi.org/10.1109/SOCDC.2009.5423838 | |||||
識別子タイプ | DOI |