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Reducing register file size through instruction pre-execution enhanced by value prediction
http://hdl.handle.net/2237/13892
http://hdl.handle.net/2237/138923ab4a498-3f81-4581-b96d-5daa5e547357
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
ando.pdf (178.6 kB)
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| アイテムタイプ | 学術雑誌論文 / Journal Article(1) | |||||
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| 公開日 | 2010-07-30 | |||||
| タイトル | ||||||
| タイトル | Reducing register file size through instruction pre-execution enhanced by value prediction | |||||
| 言語 | en | |||||
| 著者 |
Tanaka, Yusuke
× Tanaka, Yusuke× Ando, Hideki |
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| アクセス権 | ||||||
| アクセス権 | open access | |||||
| アクセス権URI | http://purl.org/coar/access_right/c_abf2 | |||||
| 権利 | ||||||
| 権利情報 | ©2009 IEEE. Personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution to servers or lists, or to reuse any copyrighted component of this work in other works must be obtained from the IEEE. | |||||
| 言語 | en | |||||
| 抄録 | ||||||
| 内容記述タイプ | Abstract | |||||
| 内容記述 | Two-step physical register deallocation (TSD) is an architectural scheme, which enhances memory-level parallelism (MLP) by pre-executing instructions. Ideally, the TSD allows MLP under the unlimited number of physical registers to be exploited, and consequently only a small register file is necessary for MLP. In practice, however, the amount of MLP exploitable is limited, because there are cases where pre-execution is not performed or timing of pre-execution is delayed. This is caused by data dependencies among the pre-executed instructions. This paper proposes the use of value prediction to solve these problems. Our way of the value prediction usage has the advantage over the conventional way of the usage for enhancing ILP, that there is no need to recover from misspeculation. Our evaluation results using SPECfp2000 benchmark show that our scheme can achieve equivalent performance to that of the previous TSD scheme without value prediction, with 75% of the register file size. | |||||
| 言語 | en | |||||
| 出版者 | ||||||
| 出版者 | IEEE | |||||
| 言語 | en | |||||
| 言語 | ||||||
| 言語 | eng | |||||
| 資源タイプ | ||||||
| 資源タイプresource | http://purl.org/coar/resource_type/c_6501 | |||||
| タイプ | journal article | |||||
| 出版タイプ | ||||||
| 出版タイプ | VoR | |||||
| 出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||
| DOI | ||||||
| 関連タイプ | isVersionOf | |||||
| 識別子タイプ | DOI | |||||
| 関連識別子 | https://doi.org/10.1109/ICCD.2009.5413149 | |||||
| ISSN | ||||||
| 収録物識別子タイプ | PISSN | |||||
| 収録物識別子 | 1063-6404 | |||||
| 書誌情報 |
en : IEEE International Conference on Computer Design(ICCD 2009) p. 238-245, 発行日 2009-10-04 |
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| フォーマット | ||||||
| 値 | application/pdf | |||||
| 著者版フラグ | ||||||
| 値 | publisher | |||||
| URI | ||||||
| 識別子 | http://hdl.handle.net/2237/13892 | |||||
| 識別子タイプ | HDL | |||||
| URI | ||||||
| 識別子 | http://dx.doi.org/10.1109/ICCD.2009.5413149 | |||||
| 識別子タイプ | DOI | |||||
