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An Improved Algorithm for the Net Assignment Problem
http://hdl.handle.net/2237/15062
http://hdl.handle.net/2237/15062d401540e-d054-4b50-a282-dcaa4d5509df
| 名前 / ファイル | ライセンス | アクション |
|---|---|---|
461.pdf (258.4 kB)
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| Item type | 学術雑誌論文 / Journal Article(1) | |||||
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| 公開日 | 2011-07-13 | |||||
| タイトル | ||||||
| タイトル | An Improved Algorithm for the Net Assignment Problem | |||||
| 言語 | en | |||||
| 著者 |
ONO, Takao
× ONO, Takao× HIRATA, Tomio |
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| アクセス権 | ||||||
| アクセス権 | open access | |||||
| アクセス権URI | http://purl.org/coar/access_right/c_abf2 | |||||
| 権利 | ||||||
| 言語 | en | |||||
| 権利情報 | Copyright (C) 2001 IEICE | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | logic emulator | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | net assignment problem | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | edge coloring | |||||
| キーワード | ||||||
| 主題Scheme | Other | |||||
| 主題 | nearly equitable edge coloring | |||||
| 抄録 | ||||||
| 内容記述 | In this paper, we consider the net assignment problem in the logic emulation system. This problem is also known as the board-level-routing problem. There are field programmable logic arrays (FPGAs) and crossbars on an emulator board. Each FPGA is connected to each crossbar. Connection requests between FPGAs are called nets, and FPGAs are interconnected through crossbars. We are required to assign each net to the suitable crossbar. This problem is known to be NP-complete in general. A polynomial time algorithm is known for a certain restricted case, in which we treat only 2-terminal nets. In this paper we propose a new polynomial time algorithm for this case. | |||||
| 言語 | en | |||||
| 内容記述タイプ | Abstract | |||||
| 出版者 | ||||||
| 言語 | en | |||||
| 出版者 | Institute of Electronics, Information and Communication Engineers | |||||
| 言語 | ||||||
| 言語 | eng | |||||
| 資源タイプ | ||||||
| 資源タイプresource | http://purl.org/coar/resource_type/c_6501 | |||||
| タイプ | journal article | |||||
| 出版タイプ | ||||||
| 出版タイプ | VoR | |||||
| 出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||
| 関連情報 | ||||||
| 関連タイプ | isVersionOf | |||||
| 識別子タイプ | URI | |||||
| 関連識別子 | http://www.ieice.org/jpn/trans_online/index.html | |||||
| ISSN | ||||||
| 収録物識別子タイプ | PISSN | |||||
| 収録物識別子 | 0916-8508 | |||||
| 書誌情報 |
en : IEICE transactions on fundamentals of electronics, communications and computer sciences 巻 E84-A, 号 5, p. 1161-1165, 発行日 2001-05-01 |
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| 著者版フラグ | ||||||
| 値 | publisher | |||||
| URI | ||||||
| 識別子 | http://www.ieice.org/jpn/trans_online/index.html | |||||
| 識別子タイプ | URI | |||||
| URI | ||||||
| 識別子 | http://hdl.handle.net/2237/15062 | |||||
| 識別子タイプ | HDL | |||||
