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We present a new design technique of RSFQ logic gates for noise reduction. In this study, we propose the use of a damping resistor shared with a junction pair composing a comparator, in addition to their individual shunt resistors increased from the standard values to increase McCumber-Stewart parameters from 1 to 4. We analyzed timing characteristics and bit error rates (BERs) of several RSFQ flip-flops composed of the proposed comparators using numerical simulation. The proposed comparator showed sharped BER curves, and improvement in timing characteristics compared to the standard comparator. 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