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A Combined Circuit for Multiplication and Inversion in ${rm GF}(2^{m})$
http://hdl.handle.net/2237/11157
http://hdl.handle.net/2237/11157f01f1b99-c7eb-4f88-ba92-dea42097da03
名前 / ファイル | ライセンス | アクション |
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getPDF_jsp.pdf (494.5 kB)
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Item type | 学術雑誌論文 / Journal Article(1) | |||||
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公開日 | 2009-02-24 | |||||
タイトル | ||||||
タイトル | A Combined Circuit for Multiplication and Inversion in ${rm GF}(2^{m})$ | |||||
言語 | en | |||||
著者 |
Kobayashi, Katsuki
× Kobayashi, Katsuki× Takagi, Naofumi× 高木, 直史 |
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アクセス権 | ||||||
アクセス権 | open access | |||||
アクセス権URI | http://purl.org/coar/access_right/c_abf2 | |||||
権利 | ||||||
言語 | en | |||||
権利情報 | Copyright © 2008 IEEE. Reprinted from IEEE Transactions on Circuits and Systems II: Express Briefs, v.55, n.11, 2008, p.1144-1148. This material is posted here with permission of the IEEE. Such permission of the IEEE does not in any way imply IEEE endorsement of any of Nagoya University’s products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | Galois field | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | inversion | |||||
キーワード | ||||||
主題Scheme | Other | |||||
主題 | multiplication | |||||
抄録 | ||||||
内容記述 | A combined circuit for multiplication and inversion in ${rm GF}(2^{m})$ is proposed. In order to develop a combined circuit, we start with combining the most significant bit first multiplication algorithm and the modified extended Euclid's algorithm by focusing on the similarities between them. Since almost all hardware components of the circuits are shared by multiplication and inversion, the combined circuit can be implemented with significantly smaller hardware than that necessary to implement both multiplication and inversion separately. By logic synthesis, the area of the proposed circuit is estimated to be approximately over 15% smaller than that of previously proposed combined multiplication/division circuits. | |||||
言語 | en | |||||
内容記述タイプ | Abstract | |||||
出版者 | ||||||
言語 | en | |||||
出版者 | IEEE | |||||
言語 | ||||||
言語 | eng | |||||
資源タイプ | ||||||
資源タイプresource | http://purl.org/coar/resource_type/c_6501 | |||||
タイプ | journal article | |||||
出版タイプ | ||||||
出版タイプ | VoR | |||||
出版タイプResource | http://purl.org/coar/version/c_970fb48d4fbd8a85 | |||||
DOI | ||||||
関連タイプ | isVersionOf | |||||
識別子タイプ | DOI | |||||
関連識別子 | https://doi.org/10.1109/TCSII.2008.2003347 | |||||
ISSN | ||||||
収録物識別子タイプ | PISSN | |||||
収録物識別子 | 1549-7747 | |||||
書誌情報 |
en : IEEE Transactions on Circuits and Systems II: Express Briefs 巻 55, 号 11, p. 1144-1148, 発行日 2008-11 |
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フォーマット | ||||||
application/pdf | ||||||
著者版フラグ | ||||||
値 | publisher | |||||
URI | ||||||
識別子 | http://hdl.handle.net/2237/11157 | |||||
識別子タイプ | HDL |