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A simple gate driver design for GaN-based switching devices with improved surge voltage and switching loss at 1 MHz operation
http://hdl.handle.net/2237/00033502
http://hdl.handle.net/2237/0003350284a2201c-d929-4ec9-826c-185a246d0745
名前 / ファイル | ライセンス | アクション |
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JJAP_sourcefile_Jodo (911.3 kB)
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Item type | 学術雑誌論文 / Journal Article(1) | |||||
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公開日 | 2021-02-09 | |||||
タイトル | ||||||
タイトル | A simple gate driver design for GaN-based switching devices with improved surge voltage and switching loss at 1 MHz operation | |||||
言語 | en | |||||
著者 |
Jodo, Shota
× Jodo, Shota× Iwaki, Toshihiro× Uchiyama, Kosuke× Islam, Md. Zahidul× Kataoka, Kensuke× Hayakasa, Yuki× Imaoka, Jun× Yamamoto, Masayoshi× Niitsu, Kiichi |
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アクセス権 | ||||||
アクセス権 | open access | |||||
アクセス権URI | http://purl.org/coar/access_right/c_abf2 | |||||
権利 | ||||||
言語 | en | |||||
権利情報 | This is the Accepted Manuscript version of an article accepted for publication in [Japanese Journal of Applied Physics].IOP Publishing Ltd is not responsible for any errors or omissions in this version of the manuscript or any version derived from it. The Version of Record is available online at [10.35848/1347-4065/abbdc7] | |||||
権利 | ||||||
言語 | en | |||||
権利情報 | “This Accepted Manuscript is available for reuse under a CC BY-NC-ND licence after the 12 month embargo period provided that all the terms of the licence are adhered to” | |||||
抄録 | ||||||
内容記述タイプ | Abstract | |||||
内容記述 | In power electronics, the impedance of reactance components increases proportionally with frequency; therefore, the sizes of reactance components can be reduced by increasing the switching frequency. Gallium nitride (GaN)-based devices have received significant attention in high-frequency applications because the figure-of-merit of GaN is superior to that of silicon (Si). However, for high-frequency operation, a trade-off relationship between the surge voltage induced by parasitic inductances, and the switching loss becomes significant. Therefore, in this study, we propose a gate driver that improves the trade-off relationship. This gate driver was obtained via the addition of simple logic circuits and capacitors to a conventional gate driver. The effectiveness of our proposed circuit was verified via SPICE simulations with Cadence Spectre using 180 nm CMOS technology. The simulation results show that by operating at 1 MHz, this circuit can help reduce the surge voltage by 12.2% and the switching loss by 14.3%. | |||||
言語 | en | |||||
内容記述 | ||||||
内容記述タイプ | Other | |||||
内容記述 | ファイル公開:2022-01-01 | |||||
言語 | ja | |||||
出版者 | ||||||
出版者 | IOP publishing | |||||
言語 | en | |||||
言語 | ||||||
言語 | eng | |||||
資源タイプ | ||||||
資源タイプ識別子 | http://purl.org/coar/resource_type/c_6501 | |||||
資源タイプ | journal article | |||||
出版タイプ | ||||||
出版タイプ | AM | |||||
出版タイプResource | http://purl.org/coar/version/c_ab4af688f83e57aa | |||||
DOI | ||||||
関連タイプ | isVersionOf | |||||
識別子タイプ | DOI | |||||
関連識別子 | https://doi.org/10.35848/1347-4065/abbdc7 | |||||
ISSN(print) | ||||||
収録物識別子タイプ | PISSN | |||||
収録物識別子 | 0021-4922 | |||||
書誌情報 |
en : Japanese Journal of Applied Physics 巻 60, 号 SA, p. SAAD02, 発行日 2021-01 |
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著者版フラグ | ||||||
値 | author |